JP2001015643A5 - - Google Patents

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Publication number
JP2001015643A5
JP2001015643A5 JP2000173780A JP2000173780A JP2001015643A5 JP 2001015643 A5 JP2001015643 A5 JP 2001015643A5 JP 2000173780 A JP2000173780 A JP 2000173780A JP 2000173780 A JP2000173780 A JP 2000173780A JP 2001015643 A5 JP2001015643 A5 JP 2001015643A5
Authority
JP
Japan
Prior art keywords
layer
apertures
spacing
substrate
microns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000173780A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001015643A (ja
JP4671470B2 (ja
Filing date
Publication date
Priority claimed from US09/330,648 external-priority patent/US6303871B1/en
Application filed filed Critical
Publication of JP2001015643A publication Critical patent/JP2001015643A/ja
Publication of JP2001015643A5 publication Critical patent/JP2001015643A5/ja
Application granted granted Critical
Publication of JP4671470B2 publication Critical patent/JP4671470B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000173780A 1999-06-11 2000-06-09 有機ランド・グリッド・アレイ・パッケージ、基板、有機基板、集積回路パッケージ及び回路アセンブリ Expired - Fee Related JP4671470B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/330,648 US6303871B1 (en) 1999-06-11 1999-06-11 Degassing hole design for olga trace impedance
US09/330648 1999-06-11

Publications (3)

Publication Number Publication Date
JP2001015643A JP2001015643A (ja) 2001-01-19
JP2001015643A5 true JP2001015643A5 (enExample) 2005-09-02
JP4671470B2 JP4671470B2 (ja) 2011-04-20

Family

ID=23290678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000173780A Expired - Fee Related JP4671470B2 (ja) 1999-06-11 2000-06-09 有機ランド・グリッド・アレイ・パッケージ、基板、有機基板、集積回路パッケージ及び回路アセンブリ

Country Status (3)

Country Link
US (1) US6303871B1 (enExample)
JP (1) JP4671470B2 (enExample)
TW (1) TW463338B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1318274A (zh) * 1998-09-17 2001-10-17 伊比登株式会社 多层叠合电路板
US6225687B1 (en) * 1999-09-02 2001-05-01 Intel Corporation Chip package with degassing holes
US20020003049A1 (en) * 1999-12-29 2002-01-10 Sanjay Dabral Inline and "Y" input-output bus topology
US6496081B1 (en) * 2001-09-28 2002-12-17 Lsi Logic Corporation Transmission equalization system and an integrated circuit package employing the same
JP3864093B2 (ja) * 2002-01-10 2006-12-27 シャープ株式会社 プリント配線基板、電波受信用コンバータおよびアンテナ装置
JP4154391B2 (ja) * 2003-01-30 2008-09-24 富士通株式会社 半導体装置
US7292452B2 (en) * 2004-06-10 2007-11-06 Intel Corporation Reference layer openings
US20060060379A1 (en) * 2004-09-20 2006-03-23 Mao Tseng F Printed circuit board structure
KR101077410B1 (ko) * 2009-05-15 2011-10-26 삼성전기주식회사 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법
US9864829B2 (en) * 2015-04-20 2018-01-09 Toshiba Memory Corporation Multilayer substrate, design method of multilayer substrate, manufacturing method of semiconductor device, and recording medium
KR102495574B1 (ko) * 2018-12-18 2023-02-03 삼성전자주식회사 반도체 패키지
US11417821B2 (en) * 2019-03-07 2022-08-16 Northrop Grumman Systems Corporation Superconductor ground plane patterning geometries that attract magnetic flux

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4859806A (en) * 1988-05-17 1989-08-22 Microelectronics And Computer Technology Corporation Discretionary interconnect
JPH0397973U (enExample) * 1990-01-29 1991-10-09
JPH07123150B2 (ja) * 1992-03-06 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション ハイブリッド半導体モジュール
US5410107A (en) * 1993-03-01 1995-04-25 The Board Of Trustees Of The University Of Arkansas Multichip module
JPH06291216A (ja) * 1993-04-05 1994-10-18 Sony Corp 基板及びセラミックパッケージ
CA2099477A1 (en) * 1993-06-30 1994-12-31 Guy M. Duxbury Printed circuit board
WO1998020557A1 (en) * 1996-11-08 1998-05-14 W.L. Gore & Associates, Inc. Method for reducing via inductance in an electronic assembly and device
US6184477B1 (en) * 1998-12-02 2001-02-06 Kyocera Corporation Multi-layer circuit substrate having orthogonal grid ground and power planes

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