JP2001014847A - クロック同期回路 - Google Patents

クロック同期回路

Info

Publication number
JP2001014847A
JP2001014847A JP11187052A JP18705299A JP2001014847A JP 2001014847 A JP2001014847 A JP 2001014847A JP 11187052 A JP11187052 A JP 11187052A JP 18705299 A JP18705299 A JP 18705299A JP 2001014847 A JP2001014847 A JP 2001014847A
Authority
JP
Japan
Prior art keywords
circuit
delay
output
clock
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11187052A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001014847A5 (enExample
Inventor
Koji Kato
光司 加藤
Masahiro Kamoshita
昌弘 鴨志田
Shigeo Oshima
成夫 大島
Hiroyuki Otake
博之 大竹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11187052A priority Critical patent/JP2001014847A/ja
Priority to KR1020000036987A priority patent/KR100354468B1/ko
Priority to US09/609,145 priority patent/US6292412B1/en
Publication of JP2001014847A publication Critical patent/JP2001014847A/ja
Publication of JP2001014847A5 publication Critical patent/JP2001014847A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP11187052A 1999-06-30 1999-06-30 クロック同期回路 Pending JP2001014847A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP11187052A JP2001014847A (ja) 1999-06-30 1999-06-30 クロック同期回路
KR1020000036987A KR100354468B1 (ko) 1999-06-30 2000-06-30 클럭 동기 회로
US09/609,145 US6292412B1 (en) 1999-06-30 2000-06-30 Clock control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11187052A JP2001014847A (ja) 1999-06-30 1999-06-30 クロック同期回路

Publications (2)

Publication Number Publication Date
JP2001014847A true JP2001014847A (ja) 2001-01-19
JP2001014847A5 JP2001014847A5 (enExample) 2005-06-30

Family

ID=16199342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11187052A Pending JP2001014847A (ja) 1999-06-30 1999-06-30 クロック同期回路

Country Status (3)

Country Link
US (1) US6292412B1 (enExample)
JP (1) JP2001014847A (enExample)
KR (1) KR100354468B1 (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002358782A (ja) * 2001-05-31 2002-12-13 Nec Corp 半導体記憶装置
US6741507B2 (en) 2002-03-20 2004-05-25 Renesas Technology Corp. Semiconductor device outputting data at a timing with reduced jitter
US6826109B2 (en) 2002-01-29 2004-11-30 Hitachi, Ltd. Semiconductor integrated circuit device with a RAM macro having two operation modes for receiving an input signal at different timings
KR100878527B1 (ko) * 2002-07-08 2009-01-13 삼성전자주식회사 Ｎａｎｄ 형 플래쉬 메모리 제어기와 제어기에서 사용되는클럭제어방법
US8228748B2 (en) 2009-04-20 2012-07-24 Samsung Electronics Co., Ltd. Semiconductor memory device having reduced power consumption during latency

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002109880A (ja) * 2000-09-28 2002-04-12 Toshiba Corp クロック同期回路
US6459628B1 (en) * 2001-04-02 2002-10-01 Advanced Micro Devices, Inc. System and method to facilitate stabilization of reference voltage signals in memory devices
JP4883850B2 (ja) * 2001-06-29 2012-02-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4005779B2 (ja) * 2001-07-03 2007-11-14 株式会社東芝 クロック同期回路
JP2003084721A (ja) * 2001-09-12 2003-03-19 Fujitsu Display Technologies Corp 表示装置用駆動回路装置とそれを利用した表示装置
US6771553B2 (en) * 2001-10-18 2004-08-03 Micron Technology, Inc. Low power auto-refresh circuit and method for dynamic random access memories
KR100477836B1 (ko) * 2002-05-30 2005-03-23 주식회사 하이닉스반도체 클럭 드라이버
JP2004005821A (ja) * 2002-05-31 2004-01-08 Toshiba Corp 同期型半導体記憶装置
US6731548B2 (en) * 2002-06-07 2004-05-04 Micron Technology, Inc. Reduced power registered memory module and method
KR100507874B1 (ko) * 2002-10-30 2005-08-17 주식회사 하이닉스반도체 클럭 동기화 회로를 구비한 동기식 반도체 메모리 장치 및클럭 동기화 회로의 클럭 트리 온/오프 제어회로
US7577048B2 (en) * 2007-12-31 2009-08-18 Icera, Inc. Memory interface
JP5730793B2 (ja) * 2012-01-17 2015-06-10 アラクサラネットワークス株式会社 ネットワーク中継装置およびその制御方法
KR102161083B1 (ko) * 2013-12-04 2020-10-05 에스케이하이닉스 주식회사 반도체 메모리 장치
US10177751B2 (en) * 2016-05-27 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Delay line with short recovery time
JP2019053444A (ja) * 2017-09-13 2019-04-04 東芝メモリ株式会社 半導体集積回路及び半導体装置
KR102833955B1 (ko) 2020-01-10 2025-07-15 삼성전자주식회사 호스트 장치로부터의 레퍼런스 클럭에 기반하여 전력 상태를 변경하도록 구성되는 스토리지 장치 및 그 동작 방법
US11456729B1 (en) 2021-03-26 2022-09-27 Analog Devices, Inc. Deskew cell for delay and pulse width adjustment

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0184457B1 (ko) * 1995-12-11 1999-04-15 김광호 반도체 메모리의 클럭 동기회로
JP3410922B2 (ja) 1996-04-23 2003-05-26 株式会社東芝 クロック制御回路
JPH1116349A (ja) * 1997-06-26 1999-01-22 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2000030456A (ja) * 1998-07-14 2000-01-28 Fujitsu Ltd メモリデバイス
JP3725715B2 (ja) * 1998-11-27 2005-12-14 株式会社東芝 クロック同期システム
JP2000311028A (ja) * 1999-04-28 2000-11-07 Hitachi Ltd 位相制御回路、半導体装置及び半導体メモリ

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002358782A (ja) * 2001-05-31 2002-12-13 Nec Corp 半導体記憶装置
US6826109B2 (en) 2002-01-29 2004-11-30 Hitachi, Ltd. Semiconductor integrated circuit device with a RAM macro having two operation modes for receiving an input signal at different timings
US6741507B2 (en) 2002-03-20 2004-05-25 Renesas Technology Corp. Semiconductor device outputting data at a timing with reduced jitter
KR100878527B1 (ko) * 2002-07-08 2009-01-13 삼성전자주식회사 Ｎａｎｄ 형 플래쉬 메모리 제어기와 제어기에서 사용되는클럭제어방법
US8228748B2 (en) 2009-04-20 2012-07-24 Samsung Electronics Co., Ltd. Semiconductor memory device having reduced power consumption during latency

Also Published As

Publication number Publication date
KR100354468B1 (ko) 2002-09-30
KR20010007603A (ko) 2001-01-26
US6292412B1 (en) 2001-09-18

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