JP2000354026A - 高速でタイミング精度の高いエッジを有するサブサンプリングクロック信号を発生させる為のクロック信号発生器 - Google Patents

高速でタイミング精度の高いエッジを有するサブサンプリングクロック信号を発生させる為のクロック信号発生器

Info

Publication number
JP2000354026A
JP2000354026A JP2000134811A JP2000134811A JP2000354026A JP 2000354026 A JP2000354026 A JP 2000354026A JP 2000134811 A JP2000134811 A JP 2000134811A JP 2000134811 A JP2000134811 A JP 2000134811A JP 2000354026 A JP2000354026 A JP 2000354026A
Authority
JP
Japan
Prior art keywords
clock signal
clock
signal
circuit
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2000134811A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000354026A5 (US06573293-20030603-C00009.png
Inventor
Robert M R Neff
ロバート・エム・アール・ネッフ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2000354026A publication Critical patent/JP2000354026A/ja
Publication of JP2000354026A5 publication Critical patent/JP2000354026A5/ja
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2000134811A 1999-05-06 2000-05-08 高速でタイミング精度の高いエッジを有するサブサンプリングクロック信号を発生させる為のクロック信号発生器 Ceased JP2000354026A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/306339 1999-05-06
US09/306,339 US6259281B1 (en) 1999-05-06 1999-05-06 Parallel analog sampling circuit and analog-to-digital converter system incorporating clock signal generator generating sub-sampling clock signals with fast and precisely-timed edges

Publications (2)

Publication Number Publication Date
JP2000354026A true JP2000354026A (ja) 2000-12-19
JP2000354026A5 JP2000354026A5 (US06573293-20030603-C00009.png) 2006-11-16

Family

ID=23184854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000134811A Ceased JP2000354026A (ja) 1999-05-06 2000-05-08 高速でタイミング精度の高いエッジを有するサブサンプリングクロック信号を発生させる為のクロック信号発生器

Country Status (3)

Country Link
US (1) US6259281B1 (US06573293-20030603-C00009.png)
EP (1) EP1050792A3 (US06573293-20030603-C00009.png)
JP (1) JP2000354026A (US06573293-20030603-C00009.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014516232A (ja) * 2011-06-10 2014-07-07 アストリアム リミテッド 非同期データストリームのアライメント

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6956423B2 (en) * 2002-02-01 2005-10-18 Agilent Technologies, Inc. Interleaved clock signal generator having serial delay and ring counter architecture
DE102005015429B3 (de) * 2005-04-04 2006-10-19 Infineon Technologies Ag Takterzeugung für einen zeitversetzt arbeitenden Analog-Digital-Wandler
US7668153B2 (en) * 2007-03-27 2010-02-23 Adc Telecommunications, Inc. Method for data converter sample clock distribution
US7564386B2 (en) 2007-11-16 2009-07-21 Agilent Technologies, Inc. Pre-processing data samples from parallelized data converters
US8749419B2 (en) * 2009-08-11 2014-06-10 Hittite Microwave Corporation ADC with enhanced and/or adjustable accuracy
CN101917194B (zh) * 2010-09-01 2013-03-20 李云初 双沿触发高速数模转换器
US8913698B2 (en) * 2011-04-11 2014-12-16 Softwaveradio, Inc. Programmable, frequency agile direct conversion digital receiver with high speed oversampling
US9461743B1 (en) * 2014-07-16 2016-10-04 Rockwell Collins, Inc. Pulse to digital detection circuit
US10072458B2 (en) * 2014-12-16 2018-09-11 Current Products Corp Remote controlled motorized wand for controlling blinds
US9979582B1 (en) 2017-07-10 2018-05-22 IQ-Analog Corp. Multi-zone analog-to-digital converter (ADC)
US10033398B1 (en) 2017-07-10 2018-07-24 IQ-Analog Corporation Multi-zone digital-to-analog converter (DAC)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4271488A (en) * 1979-04-13 1981-06-02 Tektronix, Inc. High-speed acquisition system employing an analog memory matrix
JPH04157379A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 遅延測定方式
US5649176A (en) * 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
KR100273251B1 (ko) * 1997-12-17 2001-01-15 김영환 듀티비를 보상하는 부지연신호 발생회로

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014516232A (ja) * 2011-06-10 2014-07-07 アストリアム リミテッド 非同期データストリームのアライメント

Also Published As

Publication number Publication date
US6259281B1 (en) 2001-07-10
EP1050792A2 (en) 2000-11-08
EP1050792A3 (en) 2005-01-05

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