JP2000228482A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JP2000228482A JP2000228482A JP11029042A JP2904299A JP2000228482A JP 2000228482 A JP2000228482 A JP 2000228482A JP 11029042 A JP11029042 A JP 11029042A JP 2904299 A JP2904299 A JP 2904299A JP 2000228482 A JP2000228482 A JP 2000228482A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- resin
- smd
- hybrid integrated
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子のワイ
ヤボンド実装部分を樹脂で被覆すると共にＳＭＤ部品
（表面実装部品）を導電性接着剤により実装してなる回
路基板を、ケース内に樹脂で封止して成る混成集積回路
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board in which a wire bonding mounting portion of a semiconductor element is covered with a resin and an SMD component (surface mounting component) is mounted with a conductive adhesive. The present invention relates to a sealed integrated circuit device.
【０００２】[0002]
【従来の技術】近年、混成集積回路基板上に搭載される
半導体素子等は、ワイヤーボンディング等により形成さ
れたワイヤを介してベアチップ実装される傾向にあり、
さらにこの実装部は樹脂のコート材で被覆される。この
ワイヤーボンディングを行うにあたっては、はんだはフ
ラックス等で基板を汚染する恐れがあるため敬遠され、
チップコンデンサやチップ抵抗等のＳＭＤ部品（表面実
装部品）は、Ａｇペースト等の導電性接着剤で実装され
るようになってきた。2. Description of the Related Art In recent years, semiconductor devices mounted on a hybrid integrated circuit board tend to be mounted on a bare chip via wires formed by wire bonding or the like.
Further, this mounting portion is covered with a resin coating material. When performing this wire bonding, solder is avoided because it may contaminate the substrate with flux etc.
SMD components (surface mounted components) such as chip capacitors and chip resistors have been mounted with a conductive adhesive such as Ag paste.
【０００３】そして、コート材で被覆された実装部と導
電性接着剤により実装されたＳＭＤ部品とを有する混成
集積回路基板は、樹脂のコート材で被覆されたケース内
に収納され、該回路基板と該ケースとの間をパッケージ
材としての熱硬化性樹脂（例えばエポキシ樹脂等）で充
填し固着することにより、パッケージ化される。A hybrid integrated circuit board having a mounting portion covered with a coating material and SMD components mounted with a conductive adhesive is accommodated in a case covered with a resin coating material, The space between the case and the case is filled with a thermosetting resin (for example, epoxy resin or the like) as a package material and fixed to form a package.
【０００４】[0004]
【発明が解決しようとする課題】ところで、ＳＭＤ部品
をはんだで実装した場合、はんだはせん断強度が高く、
パッケージ材の熱硬化性樹脂からの応力に対しても問題
は生じなかったが、ＳＭＤ部品をはんだの代わりにＡｇ
ペースト等の導電性接着剤で実装した場合は、該熱硬化
性樹脂からの応力（外力）に対して無視できず、ＳＭＤ
部品の接着部分が破壊する恐れがある。By the way, when SMD parts are mounted by solder, the solder has high shear strength,
There was no problem with the stress from the thermosetting resin of the package material, but the SMD parts were replaced with Ag instead of solder.
When mounted with a conductive adhesive such as a paste, the stress (external force) from the thermosetting resin cannot be ignored and the SMD
There is a risk that the bonded part of the component may be broken.
【０００５】この問題につき図４を用いて具体的に述べ
る。図４は、従来の混成集積回路基板におけるＳＭＤ部
品の実装構造を示す断面図であり、ＳＭＤ部品Ｊ１が基
板Ｊ２上に導電性接着剤Ｊ３を介して固着、搭載されて
いる。ＳＭＤ部品Ｊ１の周囲は結露防止用のシリコンゲ
ルＪ４を介してパッケージ材としての熱硬化性樹脂Ｊ５
によって被覆されている。[0005] This problem will be specifically described with reference to FIG. FIG. 4 is a cross-sectional view showing a mounting structure of an SMD component on a conventional hybrid integrated circuit board. An SMD component J1 is fixed and mounted on a substrate J2 via a conductive adhesive J3. Around the SMD component J1 is a thermosetting resin J5 as a package material via a silicon gel J4 for preventing dew condensation.
Covered by
【０００６】ここで、回路基板の周囲温度が変化する等
の場合、熱硬化性樹脂Ｊ５が温度によって変形（膨張、
収縮）する。すると、図中の白抜き矢印に示す様に、こ
の変形により熱硬化性樹脂Ｊ５からの応力が生じ、ＳＭ
Ｄ部品Ｊ１の接着部分すなわち導電性接着剤Ｊ３にせん
断応力が加わるため、ＳＭＤ部品Ｊ１の接着部分の破壊
が起こりうるのである。Here, when the ambient temperature of the circuit board changes, the thermosetting resin J5 is deformed (expanded,
Shrink). Then, as shown by a white arrow in the figure, this deformation causes a stress from the thermosetting resin J5, and SM
Since shearing stress is applied to the bonded portion of the D component J1, that is, the conductive adhesive J3, the bonded portion of the SMD component J1 may be broken.
【０００７】本発明は上記問題に鑑み、パッケージ材で
ある熱硬化性樹脂からＳＭＤ部品の接着部分に対して加
わるせん断応力を抑制することを目的とする。SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to suppress a shear stress applied to a bonding portion of an SMD component from a thermosetting resin as a package material.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するた
め、請求項１記載の発明では、一面上に、樹脂製のコー
ト材（７）で被覆された半導体素子（３）の実装部と、
導電性接着剤（５）により実装された表面実装部品
（４）とを有する回路基板が、熱硬化性樹脂（１１）を
用いてパッケージ化された混成集積回路装置において、
該表面実装部品とは非接触の状態で且つ該表面実装部品
の周囲を取り囲むように、該基板の一面から突出した樹
脂よりなるダム部（８）を形成し、このダム部によって
該熱硬化性樹脂から該表面実装部品に加わる応力を受け
止めるようにしたことを特徴としている。In order to achieve the above object, according to the first aspect of the present invention, a mounting portion of a semiconductor element (3) coated on one surface with a resin coating material (7) is provided.
In a hybrid integrated circuit device in which a circuit board having a surface mounting component (4) mounted with a conductive adhesive (5) is packaged using a thermosetting resin (11),
A dam portion (8) made of resin protruding from one surface of the substrate is formed so as to be in a non-contact state with the surface mount component and to surround the periphery of the surface mount component. The present invention is characterized in that a stress applied to the surface mount component from a resin is received.
【０００９】表面実装部品（４）の周囲を取り囲むダム
部（８）は該表面実装部品とは非接触の状態にあるか
ら、上記応力は該ダム部によっていったん受け止められ
該表面実装部品に直接伝わらず、該ダム部自体の膨張等
の該表面実装部品への影響も少ない。従って、本発明に
よれば、パッケージ材である熱硬化性樹脂から表面実装
部品の接着部分に対して加わるせん断応力を抑制するこ
とができる。Since the dam portion (8) surrounding the periphery of the surface mount component (4) is in a non-contact state with the surface mount component, the stress is once received by the dam portion and transmitted directly to the surface mount component. In addition, the influence of the expansion of the dam portion itself on the surface mount component is small. Therefore, according to the present invention, it is possible to suppress the shear stress applied from the thermosetting resin as the package material to the bonding portion of the surface mount component.
【００１０】また、ダム部（８）は表面実装部品（４）
の周囲において少なくとも応力のかかりやすい部位にあ
れば良いが、請求項２記載の発明のように、ダム部
（８）を基板（２）の一面において表面実装部品（４）
の全周囲を取り囲むように形成したものとすれば、装置
構成等の面から応力の大小を考慮する必要なく、確実に
請求項１の発明の効果を奏することができる。The dam portion (8) is a surface-mounted component (4).
The dam part (8) may be provided on the surface of the substrate (2) on one surface of the substrate (2), as long as it is located at least in a part where stress is likely to be applied around the part.
Is formed so as to surround the entire circumference of the device, the effect of the first aspect of the present invention can be reliably achieved without having to consider the magnitude of the stress from the aspect of the device configuration and the like.
【００１１】また、ダム部（８）を構成する樹脂はどの
ような樹脂でもよいが、請求項３記載の発明のように、
該ダム部をコート材（７）と同一の樹脂より形成するこ
とで、材料の兼用化や製造工程の簡素化が図れ、コスト
的に有利である。また、請求項４の発明では、ダム部
（８）と表面実装部品（４）との間に、シリコンゲル
（９）を充填したことを特徴としており、熱硬化性樹脂
（１１）が該ダム部と該表面実装部品との間に入り込む
のを防止でき、熱硬化性樹脂の変形による応力の影響を
より低減できる。Further, the resin constituting the dam portion (8) may be any resin.
By forming the dam portion from the same resin as the coating material (7), the material can be shared and the manufacturing process can be simplified, which is advantageous in cost. The invention according to claim 4 is characterized in that a silicone gel (9) is filled between the dam portion (8) and the surface mount component (4), and the thermosetting resin (11) is filled with the silicone gel (9). It can be prevented from entering between the portion and the surface mount component, and the effect of stress due to deformation of the thermosetting resin can be further reduced.
【００１２】なお、上記した括弧内の符号は、後述する
実施形態記載の具体的手段との対応関係を示す一例であ
る。Note that the reference numerals in parentheses above are examples showing the correspondence with specific means described in the embodiment described later.
【００１３】[0013]
【発明の実施の形態】以下、本発明を図に示す実施形態
について説明する。図１は本実施形態に係る混成集積回
路装置１００の概略断面を示すもので、ＳＩＰ（シング
ルインラインパッケージ）の形態に適用したものとして
述べる。回路基板１は、一面に図示しない回路パターン
（基板上電極）が形成されたセラミックまたは樹脂（ガ
ラスエポキシ等）等からなる基板２を有し、この基板２
の前記一面上に、半導体素子３やＳＭＤ部品（表面実装
部品、本例ではチップコンデンサ）４が実装され、混成
集積回路を構成している。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 1 shows a schematic cross section of a hybrid integrated circuit device 100 according to the present embodiment, which is described as being applied to a SIP (single in-line package) form. The circuit board 1 has a substrate 2 made of ceramic or resin (glass epoxy or the like) on which a circuit pattern (not shown) is formed on one surface.
The semiconductor element 3 and the SMD component (surface mount component, chip capacitor in this example) 4 are mounted on the above-mentioned one surface to constitute a hybrid integrated circuit.
【００１４】基板２の一面上に実装された半導体素子３
は、Ａｇペースト等の導電性接着剤５を介して接着され
ており、基板２の一面に形成された上記回路パターン
と、ワイヤボンディング等により形成された金やアルミ
等のワイヤ６により電気的に接続され回路を構成してい
る。基板２の一面上に実装されたＳＭＤ部品４も、半導
体素子３と同様に、導電性接着剤５によって接着され、
上記回路パターンと電気的に接続されている。Semiconductor element 3 mounted on one surface of substrate 2
Are electrically bonded by a conductive adhesive 5 such as an Ag paste or the like, and are electrically connected to the circuit pattern formed on one surface of the substrate 2 and a wire 6 such as gold or aluminum formed by wire bonding or the like. Connected to form a circuit. The SMD component 4 mounted on one surface of the substrate 2 is also bonded with the conductive adhesive 5 like the semiconductor element 3,
It is electrically connected to the circuit pattern.
【００１５】ワイヤ６にて電気的に接続された半導体素
子３には、半導体素子３およびワイヤ６を外力から保護
する目的から、エポキシ樹脂等の樹脂コート材７により
半導体素子３およびワイヤ６を完全に覆っている。な
お、導電性接着剤５で実装されているＳＭＤ部品４は、
図１では１個であるが複数個あってもよい。ここで、Ｓ
ＭＤ部品４およびその周囲の拡大構造を図２に示す。図
２において、（ａ）は上記拡大構造を基板２の一面の上
方からみたもの、（ｂ）は（ａ）中のＡ−Ａ断面図であ
る。なお、図２（ａ）中のハッチングは便宜上施したも
ので断面を示すものではない。In order to protect the semiconductor element 3 and the wire 6 from external force, the semiconductor element 3 and the wire 6 are completely connected by a resin coating material 7 such as an epoxy resin. Covered. The SMD component 4 mounted with the conductive adhesive 5 is
In FIG. 1, the number is one, but there may be a plurality. Where S
FIG. 2 shows the MD component 4 and an enlarged structure around it. 2A is a view of the enlarged structure as viewed from above one surface of the substrate 2, and FIG. 2B is a sectional view taken along line AA in FIG. The hatching in FIG. 2A is given for convenience and does not show a cross section.
【００１６】本実施形態においては、基板２の一面から
突出したダム部８が、ＳＭＤ部品４とは離間配置され
（即ち、非接触の状態で）且つＳＭＤ部品４の全周囲を
取り囲むように形成された独自の構成としている。この
ダム部８は、樹脂コート材７と同一の樹脂より形成され
ている。なお、ダム部８はＳＭＤ部品４が複数個の場合
は、各ＳＭＤ部品４毎に設けられる。In the present embodiment, a dam portion 8 protruding from one surface of the substrate 2 is formed so as to be spaced apart from the SMD component 4 (that is, in a non-contact state) and to surround the entire periphery of the SMD component 4. It has a unique configuration. This dam portion 8 is formed of the same resin as the resin coating material 7. In the case where there are a plurality of SMD components 4, the dam portion 8 is provided for each SMD component 4.
【００１７】また、図１及び図２（ｂ）に示す様に、ダ
ム部８とＳＭＤ部品４との隙間には、シリコンゲル９が
充填されている。このシリコンゲル９は、回路形成（実
装）されている部分の結露防止及び外部応力緩和を目的
としたもので、図１に示す様に、樹脂コート材７により
被覆された半導体素子３およびワイヤ６と、ダム部８お
よびＳＭＤ部品４とを包み込むように、基板２の一面を
被覆している。As shown in FIGS. 1 and 2B, the gap between the dam portion 8 and the SMD component 4 is filled with a silicon gel 9. This silicon gel 9 is intended to prevent dew condensation and relieve external stress in a portion where a circuit is formed (mounted). As shown in FIG. 1, the semiconductor element 3 and the wire 6 covered with a resin coating material 7 are used. And one surface of the substrate 2 so as to surround the dam portion 8 and the SMD component 4.
【００１８】基板２の一面上においてかかる実装構成を
有する回路基板１は、樹脂や金属等から成形されたケー
ス１０内に収納されている。回路基板１とケース１０と
の間には、本発明でいう熱硬化性樹脂（例えばエポキシ
樹脂等）であるパッケージ材１１が充填され、これによ
り回路基板１はケース１０に固定されている。また、回
路基板１におけるケース１０の開口部１０ａ側の端部に
は、図１では図示しないが、回路基板１に対して外部か
ら信号を入出力するための複数のリードピン１２（図３
参照）が接続されている。The circuit board 1 having such a mounting structure on one surface of the board 2 is housed in a case 10 formed of resin, metal, or the like. A package material 11, which is a thermosetting resin (for example, epoxy resin) according to the present invention, is filled between the circuit board 1 and the case 10, whereby the circuit board 1 is fixed to the case 10. Although not shown in FIG. 1, a plurality of lead pins 12 (not shown in FIG. 1) for inputting / outputting signals to / from the circuit board 1 from the outside are provided at an end of the case 10 of the circuit board 1 on the opening 10 a side.
Connected).
【００１９】かかる構成を有する混成集積回路装置１０
０の製造方法について、図３を参照して述べる。図３
（ａ）及び（ｂ）は本製造方法を示す工程説明図であ
る。まず、用意された基板２の一面の所定部位に、導電
性接着剤５を印刷等により塗布し、この塗布部分に半導
体素子３やＳＭＤ部品４を搭載し、固定する。そして、
半導体素子３と基板２の一面との間でワイヤボンディン
グを行い、ワイヤ６を形成する。A hybrid integrated circuit device 10 having such a configuration.
0 will be described with reference to FIG. FIG.
(A) And (b) is process explanatory drawing which shows this manufacturing method. First, a conductive adhesive 5 is applied to a predetermined portion of one surface of the prepared substrate 2 by printing or the like, and the semiconductor element 3 and the SMD component 4 are mounted on the applied portion and fixed. And
Wire bonding is performed between the semiconductor element 3 and one surface of the substrate 2 to form a wire 6.
【００２０】次に、ディスペンサや注射器及び印刷等を
用いて、樹脂コート材７を構成する樹脂をワイヤボンド
実装部の上及びＳＭＤ部品４の全周囲に配置する。その
後、この樹脂に対して加熱硬化処理を行うことにより、
樹脂コート材７及びダム部８が形成される。続いて、シ
リコンゲル９を、基板２の一面に塗布もしくはディップ
し、これを硬化することにより形成し、回路基板１を形
成する。Next, using a dispenser, a syringe, printing, or the like, the resin constituting the resin coating material 7 is disposed on the wire bond mounting portion and all around the SMD component 4. Then, by performing a heat curing treatment on this resin,
The resin coating material 7 and the dam portion 8 are formed. Subsequently, the circuit board 1 is formed by applying or dipping a silicon gel 9 on one surface of the substrate 2 and curing the same.
【００２１】次に、図３（ａ）に示す様に、この回路基
板１に、上記した複数のリードピン１２を基板２の平面
方向に一列に複数個配置する。そして、図３（ａ）及び
（ｂ）に示す様に、リードピン１２が組付けられた回路
基板１を、ケース１０内に挿入し、熱硬化性のエポキシ
樹脂等のパッケージ材１１を、ケース１０内に注入、硬
化することによって回路基板１とケース１０との間に充
填する。Next, as shown in FIG. 3A, a plurality of the above-described lead pins 12 are arranged on the circuit board 1 in a line in the plane direction of the board 2. Then, as shown in FIGS. 3A and 3B, the circuit board 1 to which the lead pins 12 are attached is inserted into the case 10, and a package material 11 such as a thermosetting epoxy resin is inserted into the case 10. The space between the circuit board 1 and the case 10 is filled by injecting and curing the inside.
【００２２】こうして、ＳＩＰタイプの上記混成集積回
路装置１００が完成する。ここで、各リードピン１２を
図示しない配線基板に接続することにより、該配線基板
に本ＳＩＰを搭載するようになっている。ところで、混
成集積回路装置１００の周囲温度が変化する等の場合、
熱硬化性樹脂であるパッケージ材１１が温度によって変
形（膨張、収縮）する。すると、パッケージ材１１は、
ケース１０内を流動するため、図１中の白抜き矢印に示
す様に、各方向に応力が生じる。この応力のうち基板２
の一面と垂直な方向以外の応力は、上記のように、従来
においては、せん断応力によるＳＭＤ部品の接着部分の
破壊を引き起こす。Thus, the SIP-type hybrid integrated circuit device 100 is completed. Here, by connecting each lead pin 12 to a wiring board (not shown), the present SIP is mounted on the wiring board. By the way, when the ambient temperature of the hybrid integrated circuit device 100 changes,
The package material 11, which is a thermosetting resin, is deformed (expanded and contracted) depending on the temperature. Then, the package material 11 becomes
Since the fluid flows in the case 10, stress is generated in each direction as shown by the white arrow in FIG. Substrate 2
As described above, in the related art, the stress other than the direction perpendicular to one surface of the SMD causes the destruction of the bonded portion of the SMD component due to shear stress.
【００２３】しかしながら、本実施形態では、ＳＭＤ部
品４の全周囲にダム部８を設け且つこのダム部８はＳＭ
Ｄ部品４とは非接触の状態にあるため、上記破壊のもと
となるパッケージ材１１からの応力は、ダム部８によっ
ていったん受け止められＳＭＤ部品４に直接伝わらず、
また、ダム部８自体の熱膨張等による応力もＳＭＤ部品
４へ影響しない。従って、パッケージ材１１からＳＭＤ
部品４の接着部分に対して加わるせん断応力を抑制する
ことができる。However, in this embodiment, the dam portion 8 is provided all around the SMD component 4 and this dam portion 8
Since it is in a non-contact state with the D component 4, the stress from the package material 11 that causes the destruction is once received by the dam portion 8 and is not directly transmitted to the SMD component 4.
Further, stress due to thermal expansion of the dam portion 8 itself does not affect the SMD component 4. Therefore, the SMD is transferred from the package material 11.
The shear stress applied to the bonded portion of the component 4 can be suppressed.
【００２４】また、ダム部８とＳＭＤ部品４との間に
は、シリコンゲル９が充填されず、熱硬化樹脂であるパ
ッケージ材１１が入り込んだ形となっていても、ダム部
の無い従来構成に比べて、上記のせん断応力を抑制する
ことができる。しかし、本実施形態のように、ダム部８
とＳＭＤ部品４との間にシリコンゲル９を充填した構成
であると、熱硬化性樹脂であるパッケージ材１１がダム
部８とＳＭＤ部品４との間に入り込むのを防止でき、も
し、パッケージ材１１が入り込んだ場合に、その入り込
んだパッケージ材１１の変形によるＳＭＤ部品４への応
力の影響を低減でき、好ましい。In addition, even if the space between the dam portion 8 and the SMD component 4 is not filled with the silicon gel 9 and the package material 11 which is a thermosetting resin enters, the conventional structure having no dam portion is provided. , The above-mentioned shear stress can be suppressed. However, as in this embodiment, the dam 8
And the SMD component 4 is filled with the silicon gel 9 to prevent the package material 11, which is a thermosetting resin, from entering between the dam portion 8 and the SMD component 4. When 11 enters, the influence of stress on the SMD component 4 due to the deformation of the package material 11 into which it enters can be reduced, which is preferable.
【００２５】また、ダム部８は基板２の一面においてＳ
ＭＤ部品４の全周囲を取り囲むように形成されている
が、ＳＭＤ部品４の周囲において少なくとも応力のかか
りやすい部位にあれば良く、ＳＭＤ部品４の周囲におい
てダム部が一部存在しない構成であってもよい。しか
し、本実施形態のように、ダム部８をＳＭＤ部品４の全
周囲を取り囲むように形成すれば、装置構成等の面から
応力の大小を考慮する必要がなく、確実に上記のせん断
応力抑制効果を発揮できる。The dam portion 8 is formed on one surface of the substrate 2 by S
Although it is formed so as to surround the entire periphery of the MD component 4, it may be located at a portion where stress is likely to be applied at least around the SMD component 4, and there is no dam part around the SMD component 4. Is also good. However, if the dam portion 8 is formed so as to surround the entire periphery of the SMD component 4 as in the present embodiment, it is not necessary to consider the magnitude of the stress from the aspect of the device configuration and the like, and the above-mentioned shear stress suppression is surely achieved. The effect can be demonstrated.
【００２６】また、ダム部８を構成する樹脂はコート材
７と同一の樹脂でなくともよく、異種の樹脂であっても
よいが、本実施形態のように、コート材７と同一の樹脂
より形成することで、材料の兼用化や製造工程の簡素化
が図れ、コスト的に有利である。このように、ダム部８
の形成上の制約としては、上述のように、ダム部８とＳ
ＭＤ部品４とが非接触状態にあること、及び、ダム部８
とＳＭＤ部品４との間を十分シリコンゲル９で埋めてい
ることが条件である。また、ダム部８の高さは、シリコ
ンゲル９の粘度及び製造方法等によって異なり、ダム部
８を形成した後（樹脂の硬化後）、上記制約条件を満足
していれば良く、特に制約しない。Further, the resin forming the dam portion 8 may not be the same resin as the coating material 7 and may be a different kind of resin. By forming, the material can be shared and the manufacturing process can be simplified, which is advantageous in cost. Thus, the dam 8
As described above, the dam 8 and the S
The MD part 4 is in a non-contact state, and the dam part 8
The condition is that the space between the SMD component 4 and the SMD component 4 is sufficiently filled with the silicon gel 9. The height of the dam portion 8 varies depending on the viscosity of the silicon gel 9, the manufacturing method, and the like. After the dam portion 8 is formed (after the resin is cured), the height of the dam portion 8 only needs to satisfy the above-described constraints, and is not particularly limited. .
【００２７】ところで、本実施形態の樹脂ダム８のよう
に、混成集積回路装置において、回路基板上に壁体を有
するものとしては、特開平６−１３４９９号公報に記載
のものがある。しかし、本実施形態が、壁体である樹脂
ダム８によってＳＭＤ部品４を単品毎に覆い、パッケー
ジ材１１の樹脂による応力を緩和してＳＭＤ部品の接着
部分のせん断破壊を抑制するものであるのに対し、上記
従来公報では、集積回路素子搭載領域の全体を壁体で囲
み、囲んだ領域内部に充填されたシリコンゲルが壁体外
部の外部リード固着領域に付着するのを防止することに
よって、外部リード用パッドの剥離防止を行うものであ
り、明らかに本実施形態とは構成及び作用効果が異なる
ものである。Incidentally, in the hybrid integrated circuit device having a wall on a circuit board, such as the resin dam 8 of the present embodiment, there is one described in Japanese Patent Application Laid-Open No. Hei 6-13499. However, in the present embodiment, the SMD components 4 are individually covered by the resin dams 8 serving as walls, and the stress caused by the resin of the package material 11 is relaxed to suppress the shear failure of the bonded portions of the SMD components. On the other hand, in the above conventional publication, the entire integrated circuit element mounting area is surrounded by a wall, and silicon gel filled in the enclosed area is prevented from adhering to an external lead fixing area outside the wall, This is to prevent peeling of the external lead pad, and is obviously different in configuration, function and effect from this embodiment.
【００２８】すなわち、上記従来公報の構成としたとこ
ろで、集積回路素子搭載領域に銀ペースト等により搭載
される素子には、パッケージ材としての熱硬化性樹脂か
らの応力が伝わり、素子の接着部分にせん断応力がかか
る。さらに言うならば、上記従来公報では、チップコン
デンサなどのＳＭＤ部品は、半田固着されたものであ
り、本発明のＳＭＤ部品のように、導電性接着剤で接着
された構成に特有の上記課題は発生しない。That is, in the configuration of the above-mentioned conventional publication, stress from the thermosetting resin as a package material is transmitted to the element mounted on the integrated circuit element mounting area with silver paste or the like, and the element is bonded to the bonding portion. Shear stress is applied. More specifically, in the above-mentioned conventional publication, the SMD component such as a chip capacitor is fixed by soldering, and the above-described problem peculiar to the configuration bonded with a conductive adhesive like the SMD component of the present invention is as follows. Does not occur.
【００２９】なお、本発明は上記実施形態に示したＳＩ
Ｐに限定されるものではなく、例えば、ＤＩＰ等のパッ
ケージ形態であってもよい。要するに、本発明は、半導
体素子のワイヤボンド実装部分を樹脂で被覆すると共に
ＳＭＤ部品（表面実装部品）を導電性接着剤により実装
してなる回路基板を、ケース内に樹脂で封止して成る混
成集積回路装置に、適用可能なものである。The present invention relates to the SI shown in the above embodiment.
It is not limited to P, but may be a package form such as DIP. In short, the present invention comprises a circuit board formed by covering a wire bond mounting portion of a semiconductor element with a resin and mounting an SMD component (surface mounting component) with a conductive adhesive in a case. The present invention is applicable to a hybrid integrated circuit device.
【図１】本発明の実施形態に係る混成集積回路装置の概
略断面である。FIG. 1 is a schematic cross section of a hybrid integrated circuit device according to an embodiment of the present invention.
【図２】図１におけるＳＭＤ部品およびその周囲の拡大
構造を示す図である。FIG. 2 is a diagram illustrating an SMD component and an enlarged structure around the SMD component in FIG. 1;
【図３】上記実施形態に係る混成集積回路装置の製造方
法を示す工程説明図である。FIG. 3 is a process diagram illustrating a method for manufacturing the hybrid integrated circuit device according to the embodiment.
【図４】従来の混成集積回路基板におけるＳＭＤ部品実
装構造を示す断面図である。FIG. 4 is a cross-sectional view showing an SMD component mounting structure on a conventional hybrid integrated circuit board.
１…回路基板、２…基板、３…半導体素子、４…ＳＭＤ
部品、５…導電性接着剤、６…ワイヤ、７…樹脂コート
材、８…ダム部、９…シリコンゲル、１０…ケース、１
１…パッケージ材。DESCRIPTION OF SYMBOLS 1 ... Circuit board, 2 ... Board, 3 ... Semiconductor element, 4 ... SMD
Parts, 5: conductive adhesive, 6: wire, 7: resin coating material, 8: dam part, 9: silicon gel, 10: case, 1
1. Package material.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 斎藤 光弘 愛知県刈谷市昭和町１丁目１番地 株式会 社デンソー内 Ｆターム(参考） 4M109 AA02 BA04 CA02 CA06 DB07 DB09 EA02 ED04 EE02 GA02 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Mitsuhiro Saito 1-1-1 Showa-cho, Kariya-shi, Aichi F-term in DENSO Corporation (Reference) 4M109 AA02 BA04 CA02 CA06 DB07 DB09 EA02 ED04 EE02 GA02
Claims (4)
して実装された半導体素子（３）、および導電性接着剤
（５）を介して実装された表面実装部品（４）を搭載す
るとともに、前記半導体素子及び前記ワイヤを樹脂製の
コート材（７）にて被覆してなる回路基板（１）を有
し、 この回路基板をケース（１０）内に収納するとともに、
前記回路基板と前記ケースとの間を熱硬化性樹脂（１
１）で充填し固着するようにした混成集積回路装置にお
いて、 前記表面実装部品とは非接触の状態で且つ前記表面実装
部品の周囲を取り囲むように、前記基板の一面から突出
した樹脂よりなるダム部（８）が形成されており、 このダム部によって前記熱硬化性樹脂から前記表面実装
部品に加わる応力を受け止めるようにしたことを特徴と
する混成集積回路装置。1. A semiconductor element (3) mounted on one surface of a substrate (2) via wires (6) and a surface mounted component (4) mounted on a conductive adhesive (5). A circuit board (1) comprising the semiconductor element and the wire covered with a resin coating material (7) while being mounted, and the circuit board is housed in a case (10).
A thermosetting resin (1) is provided between the circuit board and the case.
In the hybrid integrated circuit device filled and fixed in 1), a dam made of a resin protruding from one surface of the substrate so as to be in a non-contact state with the surface mount component and to surround a periphery of the surface mount component. A hybrid integrated circuit device, wherein a portion (8) is formed, and the dam portion receives stress applied to the surface mount component from the thermosetting resin.
一面において前記表面実装部品（４）の全周囲を取り囲
むように形成されていることを特徴とする請求項１に記
載の混成集積回路装置。2. The device according to claim 1, wherein the dam portion is formed on one surface of the substrate so as to surround the entire periphery of the surface mount component. Hybrid integrated circuit device.
と同一の樹脂より形成されていることを特徴とする請求
項１または２に記載の混成集積回路装置。3. The dam member (8) is provided with the coating material (7).
3. The hybrid integrated circuit device according to claim 1, wherein the hybrid integrated circuit device is formed of the same resin as that of the hybrid integrated circuit device.
（４）との間には、シリコンゲル（９）が充填されてい
ることを特徴とする請求項１ないし３のいずれか１つに
記載の混成集積回路装置。4. The silicon gel (9) is filled between the dam part (8) and the surface mount component (4). 3. The hybrid integrated circuit device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02904299A JP3975596B2 (en) | 1999-02-05 | 1999-02-05 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02904299A JP3975596B2 (en) | 1999-02-05 | 1999-02-05 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000228482A true JP2000228482A (en) | 2000-08-15 |
| JP3975596B2 JP3975596B2 (en) | 2007-09-12 |
Family
ID=12265351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02904299A Expired - Lifetime JP3975596B2 (en) | 1999-02-05 | 1999-02-05 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3975596B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129826A (en) * | 2008-11-28 | 2010-06-10 | Denso Corp | Electronic apparatus and method of manufacturing the same |
| JP2010141077A (en) * | 2008-12-11 | 2010-06-24 | Sanken Electric Co Ltd | Electronic circuit device |
| JP2012195615A (en) * | 2012-07-10 | 2012-10-11 | Denso Corp | Electronic apparatus |
| JP2014506395A (en) * | 2010-12-14 | 2014-03-13 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for manufacturing an electronic unit having a molded body |
| CN110600432A (en) * | 2019-05-27 | 2019-12-20 | 华为技术有限公司 | Packaging structure and mobile terminal |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104812193B (en) * | 2014-01-24 | 2017-11-21 | 台达电子企业管理（上海）有限公司 | A kind of encapsulating power supply |
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1999
- 1999-02-05 JP JP02904299A patent/JP3975596B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129826A (en) * | 2008-11-28 | 2010-06-10 | Denso Corp | Electronic apparatus and method of manufacturing the same |
| JP2010141077A (en) * | 2008-12-11 | 2010-06-24 | Sanken Electric Co Ltd | Electronic circuit device |
| US8237532B2 (en) | 2008-12-11 | 2012-08-07 | Sanken Electric Co., Ltd. | Electronic circuit device |
| JP2014506395A (en) * | 2010-12-14 | 2014-03-13 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for manufacturing an electronic unit having a molded body |
| JP2012195615A (en) * | 2012-07-10 | 2012-10-11 | Denso Corp | Electronic apparatus |
| CN110600432A (en) * | 2019-05-27 | 2019-12-20 | 华为技术有限公司 | Packaging structure and mobile terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3975596B2 (en) | 2007-09-12 |
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