JP2000223681A5 - 基板の製造方法 - Google Patents

基板の製造方法 Download PDF

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JP2000223681A5
JP2000223681A5 JP1999025481A JP2548199A JP2000223681A5 JP 2000223681 A5 JP2000223681 A5 JP 2000223681A5 JP 1999025481 A JP1999025481 A JP 1999025481A JP 2548199 A JP2548199 A JP 2548199A JP 2000223681 A5 JP2000223681 A5 JP 2000223681A5
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Prior art keywords
layer
substrate manufacturing
bonded substrate
substrate
manufacturing
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JP1999025481A
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JP4313874B2 (ja
JP2000223681A (ja
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Priority claimed from JP02548199A external-priority patent/JP4313874B2/ja
Priority to JP02548199A priority Critical patent/JP4313874B2/ja
Priority to EP00300720A priority patent/EP1026728A3/en
Priority to US09/496,130 priority patent/US6624047B1/en
Priority to KR10-2000-0005286A priority patent/KR100371450B1/ko
Priority to CN00105306A priority patent/CN1272684A/zh
Publication of JP2000223681A publication Critical patent/JP2000223681A/ja
Publication of JP2000223681A5 publication Critical patent/JP2000223681A5/ja
Publication of JP4313874B2 publication Critical patent/JP4313874B2/ja
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【特許請求の範囲】
【請求項1】 貼り合わせ基板の製造方法であって、
内部に多孔質層を有し、その上に第1の層を有し、その上に更に第2の層を有する第1の基板を作成する第1工程と、
前記第1の基板の主面と第2の基板とを貼り合せて、貼り合わせ基板を作成する第2工程と、
前記貼り合わせ基板に化学的処理を施すことにより、前記第1の層の外周端の少なくとも一部を前記貼り合わせ基板の内部方向に後退させる第3工程と、
を含むことを特徴とする貼り合わせ基板の製造方法。
【請求項】 前記第3工程は、前記第2工程により作成された貼り合わせ基板の前記第1の層の外周部の少なくとも一部を酸化させる工程を含むことを特徴とする請求項に記載の貼り合わせ基板の製造方法。
【請求項】 前記第3工程は、前記第2工程により作成された貼り合わせ基板の前記第1の層の外周端の少なくとも一部をエッチングする工程を含むことを特徴とする請求項に記載の貼り合わせ基板の製造方法。
【請求項】 前記第1工程は、Si基板に陽極化成処理を施すことにより前記多孔質層を形成する工程を含むことを特徴とする請求項に記載の貼り合わせ基板の製造方法。
【請求項】 前記第1工程は、
前記多孔質層の上に前記第1の層としてのSi層を形成する工程と、
前記Si層の表面を熱酸化させることにより、前記Si層上に前記第2の層としてのSiO2層を形成する工程と、
を含むことを特徴とする請求項に記載の貼り合わせ基板の製造方法。
【請求項】 基板の製造方法であって、
請求項1乃至請求項のいずれか1項に記載の貼り合わせ基板の製造方法により貼り合わせ基板を作成する工程と、
作成された貼り合わせ基板を前記多孔質層の部分で2枚の基板に分離する工程と、
を含むことを特徴とする基板の製造方法。
【請求項】 前記分離工程では、前記貼り合わせ基板の貼り合わせ面付近に向けて流体を噴射し、該流体により前記貼り合わせ基板を前記多孔質層の部分で2枚の基板に分離することを特徴とする請求項に記載の基板の製造方法。
JP02548199A 1999-02-02 1999-02-02 基板の製造方法 Expired - Fee Related JP4313874B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP02548199A JP4313874B2 (ja) 1999-02-02 1999-02-02 基板の製造方法
EP00300720A EP1026728A3 (en) 1999-02-02 2000-01-31 Substrate and method of manufacturing the same
US09/496,130 US6624047B1 (en) 1999-02-02 2000-02-01 Substrate and method of manufacturing the same
CN00105306A CN1272684A (zh) 1999-02-02 2000-02-02 衬底及其制造方法
KR10-2000-0005286A KR100371450B1 (ko) 1999-02-02 2000-02-02 기판 및 그의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02548199A JP4313874B2 (ja) 1999-02-02 1999-02-02 基板の製造方法

Publications (3)

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JP2000223681A JP2000223681A (ja) 2000-08-11
JP2000223681A5 true JP2000223681A5 (ja) 2006-03-16
JP4313874B2 JP4313874B2 (ja) 2009-08-12

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JP02548199A Expired - Fee Related JP4313874B2 (ja) 1999-02-02 1999-02-02 基板の製造方法

Country Status (5)

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US (1) US6624047B1 (ja)
EP (1) EP1026728A3 (ja)
JP (1) JP4313874B2 (ja)
KR (1) KR100371450B1 (ja)
CN (1) CN1272684A (ja)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2774511B1 (fr) * 1998-01-30 2002-10-11 Commissariat Energie Atomique Substrat compliant en particulier pour un depot par hetero-epitaxie
US6616854B2 (en) * 2001-12-17 2003-09-09 Motorola, Inc. Method of bonding and transferring a material to form a semiconductor device
KR100446624B1 (ko) * 2002-02-27 2004-09-04 삼성전자주식회사 양극접합 구조체 및 그 제조방법
KR100476901B1 (ko) * 2002-05-22 2005-03-17 삼성전자주식회사 소이 반도체기판의 형성방법
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
JP3944087B2 (ja) * 2003-01-21 2007-07-11 株式会社東芝 素子形成用基板の製造方法
US7105448B2 (en) * 2003-02-28 2006-09-12 Semiconductor Energy Laboratory Co., Ltd. Method for peeling off semiconductor element and method for manufacturing semiconductor device
US7122095B2 (en) * 2003-03-14 2006-10-17 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for forming an assembly for transfer of a useful layer
EP1634296A4 (en) * 2003-06-09 2007-02-14 Nantero Inc NON-VOLATILE ELECTROMECHANICAL FIELD EFFECT BLOCKS AND CIRCUITS THEREFOR AND METHOD FOR THEIR PRODUCTION
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
JP4838504B2 (ja) * 2004-09-08 2011-12-14 キヤノン株式会社 半導体装置の製造方法
ATE420461T1 (de) * 2004-11-09 2009-01-15 Soitec Silicon On Insulator Verfahren zum herstellen von zusammengesetzten wafern
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
JP2006173354A (ja) * 2004-12-15 2006-06-29 Canon Inc Soi基板の製造方法
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
US7820495B2 (en) * 2005-06-30 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
FR2899594A1 (fr) 2006-04-10 2007-10-12 Commissariat Energie Atomique Procede d'assemblage de substrats avec traitements thermiques a basses temperatures
KR101443580B1 (ko) * 2007-05-11 2014-10-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Soi구조를 갖는 기판
TWI493609B (zh) * 2007-10-23 2015-07-21 Semiconductor Energy Lab 半導體基板、顯示面板及顯示裝置的製造方法
FR2939962B1 (fr) * 2008-12-15 2011-03-18 Soitec Silicon On Insulator Procede d'amincissement d'une structure.
JP5244650B2 (ja) * 2009-02-26 2013-07-24 信越半導体株式会社 Soiウェーハの製造方法
US8476165B2 (en) * 2009-04-01 2013-07-02 Tokyo Electron Limited Method for thinning a bonding wafer
EP2246882B1 (en) * 2009-04-29 2015-03-04 Soitec Method for transferring a layer from a donor substrate onto a handle substrate
KR101105918B1 (ko) * 2009-11-30 2012-01-17 주식회사 엘지실트론 질화물 반도체 소자의 제조방법
US20120129318A1 (en) * 2010-11-24 2012-05-24 Semiconductor Energy Laboratory Co., Ltd. Atmospheric pressure plasma etching apparatus and method for manufacturing soi substrate
FR2969373B1 (fr) * 2010-12-20 2013-07-19 St Microelectronics Crolles 2 Procede d'assemblage de deux plaques et dispositif correspondant
US9393669B2 (en) * 2011-10-21 2016-07-19 Strasbaugh Systems and methods of processing substrates
GB201211309D0 (en) * 2012-06-26 2012-08-08 Fujifilm Mfg Europe Bv Process for preparing membranes
US9610669B2 (en) 2012-10-01 2017-04-04 Strasbaugh Methods and systems for use in grind spindle alignment
US9457446B2 (en) 2012-10-01 2016-10-04 Strasbaugh Methods and systems for use in grind shape control adaptation
CN103545239B (zh) * 2013-09-17 2017-01-11 新磊半导体科技(苏州)有限公司 一种基于薄膜型的外延片剥离工艺
US9741918B2 (en) 2013-10-07 2017-08-22 Hypres, Inc. Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit
US9209069B2 (en) * 2013-10-15 2015-12-08 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI substrate with reduced interface conductivity
US10079170B2 (en) 2014-01-23 2018-09-18 Globalwafers Co., Ltd. High resistivity SOI wafers and a method of manufacturing thereof
US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
US9853133B2 (en) 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
US10312134B2 (en) 2014-09-04 2019-06-04 Globalwafers Co., Ltd. High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
US10381260B2 (en) 2014-11-18 2019-08-13 GlobalWafers Co., Inc. Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers
EP3573094B1 (en) 2014-11-18 2023-01-04 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
WO2016081367A1 (en) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
FR3032555B1 (fr) * 2015-02-10 2018-01-19 Soitec Procede de report d'une couche utile
CN107533953B (zh) 2015-03-03 2021-05-11 环球晶圆股份有限公司 具有可控膜应力的在硅衬底上沉积电荷捕获多晶硅膜的方法
WO2016149113A1 (en) 2015-03-17 2016-09-22 Sunedison Semiconductor Limited Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
CN114496732B (zh) 2015-06-01 2023-03-03 环球晶圆股份有限公司 制造绝缘体上硅锗的方法
WO2016196060A1 (en) 2015-06-01 2016-12-08 Sunedison Semiconductor Limited A method of manufacturing semiconductor-on-insulator
EP3378094B1 (en) 2015-11-20 2021-09-15 Globalwafers Co., Ltd. Manufacturing method of smoothing a semiconductor surface
US10622247B2 (en) 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
US10468294B2 (en) 2016-02-19 2019-11-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
US11114332B2 (en) 2016-03-07 2021-09-07 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
US10026642B2 (en) 2016-03-07 2018-07-17 Sunedison Semiconductor Limited (Uen201334164H) Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof
WO2017155804A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
EP3758050A1 (en) 2016-03-07 2020-12-30 GlobalWafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
US10867836B2 (en) * 2016-05-02 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer stack and fabrication method thereof
SG11201810486VA (en) 2016-06-08 2018-12-28 Globalwafers Co Ltd High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
EP3533081B1 (en) 2016-10-26 2021-04-14 GlobalWafers Co., Ltd. High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
EP3549162B1 (en) 2016-12-05 2022-02-02 GlobalWafers Co., Ltd. High resistivity silicon-on-insulator structure and method of manufacture thereof
EP3653761B1 (en) 2016-12-28 2024-02-28 Sunedison Semiconductor Limited Silicon wafers with intrinsic gettering and gate oxide integrity yield
EP3989272A1 (en) 2017-07-14 2022-04-27 Sunedison Semiconductor Limited Method of manufacture of a semiconductor on insulator structure
JP7160943B2 (ja) 2018-04-27 2022-10-25 グローバルウェーハズ カンパニー リミテッド 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成
CN112262467B (zh) 2018-06-08 2024-08-09 环球晶圆股份有限公司 将硅薄层移转的方法
JP7242362B2 (ja) * 2019-03-18 2023-03-20 キオクシア株式会社 半導体装置の製造方法
CN110060958B (zh) * 2019-04-22 2020-05-19 长江存储科技有限责任公司 半导体结构及半导体工艺方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3898107A (en) * 1973-12-03 1975-08-05 Rca Corp Method of making a junction-isolated semiconductor integrated circuit device
JP2608351B2 (ja) 1990-08-03 1997-05-07 キヤノン株式会社 半導体部材及び半導体部材の製造方法
JP3237888B2 (ja) * 1992-01-31 2001-12-10 キヤノン株式会社 半導体基体及びその作製方法
JP3293736B2 (ja) * 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JP3257580B2 (ja) 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法
US5668045A (en) * 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
KR0171067B1 (ko) 1994-12-05 1999-03-30 문정환 단결정 soi웨이퍼 제조방법
JP3381443B2 (ja) * 1995-02-02 2003-02-24 ソニー株式会社 基体から半導体層を分離する方法、半導体素子の製造方法およびsoi基板の製造方法
KR0168348B1 (ko) * 1995-05-11 1999-02-01 김광호 Soi 기판의 제조방법
JPH0964321A (ja) * 1995-08-24 1997-03-07 Komatsu Electron Metals Co Ltd Soi基板の製造方法
CN1132223C (zh) * 1995-10-06 2003-12-24 佳能株式会社 半导体衬底及其制造方法
US6090688A (en) * 1996-11-15 2000-07-18 Komatsu Electronic Metals Co., Ltd. Method for fabricating an SOI substrate
EP0851513B1 (en) * 1996-12-27 2007-11-21 Canon Kabushiki Kaisha Method of producing semiconductor member and method of producing solar cell
SG71094A1 (en) * 1997-03-26 2000-03-21 Canon Kk Thin film formation using laser beam heating to separate layers
SG63832A1 (en) 1997-03-26 1999-03-30 Canon Kk Substrate and production method thereof
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same

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