JP2000223575A5 - - Google Patents
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- Publication number
- JP2000223575A5 JP2000223575A5 JP1999020277A JP2027799A JP2000223575A5 JP 2000223575 A5 JP2000223575 A5 JP 2000223575A5 JP 1999020277 A JP1999020277 A JP 1999020277A JP 2027799 A JP2027799 A JP 2027799A JP 2000223575 A5 JP2000223575 A5 JP 2000223575A5
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- wiring
- supply wiring
- region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 description 42
- 230000005669 field effect Effects 0.000 description 20
- 238000000034 method Methods 0.000 description 15
- 239000000758 substrate Substances 0.000 description 11
- 239000012535 impurity Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000003014 reinforcing effect Effects 0.000 description 2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11020277A JP2000223575A (ja) | 1999-01-28 | 1999-01-28 | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11020277A JP2000223575A (ja) | 1999-01-28 | 1999-01-28 | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000223575A JP2000223575A (ja) | 2000-08-11 |
| JP2000223575A5 true JP2000223575A5 (enExample) | 2006-01-26 |
Family
ID=12022687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11020277A Pending JP2000223575A (ja) | 1999-01-28 | 1999-01-28 | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000223575A (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100667597B1 (ko) | 2005-02-07 | 2007-01-11 | 삼성전자주식회사 | 매크로 셀의 전원 라인 배치 구조 및 매크로 셀과 파워매시의 결합 구조 |
| JP2007165670A (ja) * | 2005-12-15 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 半導体回路装置およびその設計方法 |
| US8063415B2 (en) | 2007-07-25 | 2011-11-22 | Renesas Electronics Corporation | Semiconductor device |
| CN114898790A (zh) * | 2016-01-29 | 2022-08-12 | 三星电子株式会社 | 用于选择性地执行隔离功能的半导体器件及其布局替代方法 |
| CN112567507B (zh) * | 2018-08-28 | 2024-07-05 | 株式会社索思未来 | 半导体集成电路装置 |
| JP7363921B2 (ja) * | 2019-12-05 | 2023-10-18 | 株式会社ソシオネクスト | 半導体装置 |
| CN114492283B (zh) * | 2020-11-11 | 2025-08-01 | Oppo广东移动通信有限公司 | 配置芯片的方法及装置、设备、存储介质 |
| WO2024116853A1 (ja) * | 2022-11-29 | 2024-06-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
-
1999
- 1999-01-28 JP JP11020277A patent/JP2000223575A/ja active Pending
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