JP2000214216A - Semiconductor inspecting device - Google Patents

Semiconductor inspecting device

Info

Publication number
JP2000214216A
JP2000214216A JP11016620A JP1662099A JP2000214216A JP 2000214216 A JP2000214216 A JP 2000214216A JP 11016620 A JP11016620 A JP 11016620A JP 1662099 A JP1662099 A JP 1662099A JP 2000214216 A JP2000214216 A JP 2000214216A
Authority
JP
Japan
Prior art keywords
semiconductor
wiring pattern
height
inspection
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11016620A
Other languages
Japanese (ja)
Inventor
Yuji Fujita
祐治 藤田
Toshihiro Hachiya
登志広 八矢
Morio Muramatsu
盛生 村松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11016620A priority Critical patent/JP2000214216A/en
Publication of JP2000214216A publication Critical patent/JP2000214216A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

PROBLEM TO BE SOLVED: To ensure the connection reliability of a semiconductor by allowing an insulation film and a wiring pattern to be elastically deformed according to the fluctuation of the height of a salient electrode that is formed at an input/ output terminal. SOLUTION: A semiconductor 21 is retained by suction force F of a collet 27 and is moved to a specific position, and the salient electrode 24 is brought into contact with a wiring pattern 25. The height of the salient electrode 24 scatters depending on its formation method. However, the reduction in the height irregularities is limited and a height scattering of approximately ±5 μremains. When the salient electrode 24 that is subjected to a flattening process is brought into contact with the wiring pattern 25, the wiring pattern 25 and an insulation film 26 are elastically deformed so that a height, irregularities of approximately ±5 μ can be absorbed. The electrical connection of all salient electrodes 24 and the wiring patterns 25 are secured by the elastic deformation, thus inspecting the function of the semiconductor 21. By removing the semiconductor 21 due to suction force F of a collet 27 after inspection is completed, the wiring pattern 25 and the insulation film 26 that have been elastically deformed return to a shape before inspection.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体検査装置に係
り、特に接続信頼性に優れた半導体検査装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor inspection device, and more particularly to a semiconductor inspection device having excellent connection reliability.

【0002】[0002]

【従来の技術】従来の半導体検査装置として特開平7−
221146号公報の例を図2を用いて説明する。半導
体21の表面に形成された入出力パッド22と、コンタ
クトシート16の表面に形成されたバンプ17が相対す
るように半導体21を配置する。次に、フタ19を半導
体21の上面からかぶせ、ネジ20を締める。この締付
け力は、半導体21を介してコンタクトシート16、お
よび弾性体12へ伝わる。コンタクトシート16と弾性
体12は弾性変形するので、半導体21の傾きや表面の
反りに追従するようにコンタクトシート16が変形す
る。
2. Description of the Related Art A conventional semiconductor inspection apparatus is disclosed in
An example of Japanese Patent Publication No. 221146 will be described with reference to FIG. The semiconductor 21 is arranged so that the input / output pads 22 formed on the surface of the semiconductor 21 and the bumps 17 formed on the surface of the contact sheet 16 face each other. Next, the lid 19 is covered from above the semiconductor 21 and the screw 20 is tightened. This tightening force is transmitted to the contact sheet 16 and the elastic body 12 via the semiconductor 21. Since the contact sheet 16 and the elastic body 12 are elastically deformed, the contact sheet 16 is deformed so as to follow the inclination of the semiconductor 21 and the warpage of the surface.

【0003】その結果、バンプ17と入出力パッド22
の間に一定の接触圧力を確保できるので、低抵抗かつ安
定した電気的接触を実現できる。電気信号は、バンプ1
7から、コンタクトシート16の外周へ向かって形成さ
れた配線パターンを通り、その外側に設けられたソケッ
トコネクタ15へ伝送される。さらに、ベース10の内
部に形成された配線層、ベース10の底面に設けられた
ピン11を通って検査用配線基板23へ伝送され、以上
の装置により半導体21の品質をチェックすることがで
きる。
As a result, the bump 17 and the input / output pad 22
A constant contact pressure can be ensured during the contact, so that low-resistance and stable electrical contact can be realized. Electrical signal is bump 1
7, the signal is transmitted to the socket connector 15 provided outside through the wiring pattern formed toward the outer periphery of the contact sheet 16. Further, the light is transmitted to the inspection wiring board 23 through the wiring layer formed inside the base 10 and the pins 11 provided on the bottom surface of the base 10, and the quality of the semiconductor 21 can be checked by the above apparatus.

【0004】[0004]

【発明が解決しようとする課題】一般に低価格で入手で
きる半導体21の入出力パッド22はアルミ蒸着膜から
なる。従来例では、バンプ17の先端に鋭角で細かい突
起が形成されており、この突起が入出力パッド22の表
面のアルミ酸化膜を破ることにより電気的接触を得る。
多数の半導体21を検査する場合は、検査のたびに突起
が摩耗するので、アルミ酸化膜を破る能力が徐々に失わ
れ、接続抵抗が上昇し検査条件が不安定となる。
Generally, the input / output pad 22 of the semiconductor 21 which can be obtained at a low price is made of an aluminum evaporated film. In the conventional example, an acute and fine projection is formed at the tip of the bump 17, and the projection breaks the aluminum oxide film on the surface of the input / output pad 22 to obtain electrical contact.
When a large number of semiconductors 21 are inspected, the projections are worn each time the inspection is performed, so that the ability to break the aluminum oxide film is gradually lost, the connection resistance increases, and the inspection conditions become unstable.

【0005】また、検査終了後の半導体21の多くは、
金またはアルミのワイヤボンディングにより搭載基板と
電気的に接続する。または、金バンプを入出力パッド2
2へ取り付けた後、接着樹脂や異方導電性フィルムを介
して基板へ搭載する。上記従来の検査方法によると、検
査時のバンプ接触による損傷が入出力パッド22のアル
ミ表面に残っており、このためワイヤボンディングや金
バンプボンディングの接着強度が低下する。半導体の高
集積化・高機能化と共に、入出力パッド22は多ピン化
・狭ピッチ化するため、パッド面積はさらに縮小する傾
向にあり、微小な損傷でも著しい強度低下を引き起こす
可能性ある。
[0005] Further, most of the semiconductor 21 after the inspection is completed
It is electrically connected to the mounting substrate by gold or aluminum wire bonding. Or gold bumps on input / output pad 2
After mounting on the substrate 2, it is mounted on a substrate via an adhesive resin or an anisotropic conductive film. According to the above-described conventional inspection method, damage due to bump contact at the time of inspection remains on the aluminum surface of the input / output pad 22, so that the bonding strength of wire bonding or gold bump bonding decreases. As semiconductors become more highly integrated and more sophisticated, the number of pins of the input / output pads 22 becomes smaller and the pitch becomes narrower. Therefore, the pad area tends to be further reduced, and even a minute damage may cause a significant decrease in strength.

【0006】本発明の目的は、安定した接続抵抗による
半導体検査を実現し、検査後の半導体の接続信頼性を確
保するための半導体検査装置を提供することにある。
An object of the present invention is to provide a semiconductor inspection apparatus for realizing a semiconductor inspection with a stable connection resistance and ensuring the connection reliability of a semiconductor after the inspection.

【0007】[0007]

【課題を解決するための手段】本発明に係る半導体検査
装置は、半導体の入出力端子に複数の突起電極を形成
し、この突起電極を介して電気的接続を得る半導体検査
装置において、少なくとも突起電極の配列領域を含むよ
うに配置された可撓性の絶縁フィルムと、絶縁フイルム
上に形成された配線パターンとを設ける。半導体を検査
する際は、突起電極の高さのばらつきに応じて絶縁フィ
ルムまたは配線パターンが弾性変形するので、突起電極
と配線パターンの接触面の形状および面積は一定に保た
れる。また、半導体の入出力端子には予め突起電極が形
成されているので、検査の際に入出力端子表面のアルミ
酸化膜を破る必要はなくなり、検査を繰り返しても接触
部分の摩耗による接続抵抗の上昇の問題は生じない。よ
って、多数の半導体を検査しても接続抵抗を安定に保つ
ことができる。また、入出力端子のアルミ表面は検査に
よる損傷を受けないので、検査終了後の半導体について
も接続信頼性の劣化は生じない。
A semiconductor inspection apparatus according to the present invention comprises a plurality of projection electrodes formed on input / output terminals of a semiconductor and an electrical connection through the projection electrodes. A flexible insulating film disposed so as to include an electrode arrangement region and a wiring pattern formed on the insulating film are provided. When inspecting a semiconductor, the insulating film or the wiring pattern is elastically deformed according to the variation in the height of the bump electrode, so that the shape and area of the contact surface between the bump electrode and the wiring pattern are kept constant. In addition, since the protruding electrodes are formed on the input / output terminals of the semiconductor in advance, it is not necessary to break the aluminum oxide film on the surface of the input / output terminals during the inspection. The problem of rising does not arise. Therefore, even if a large number of semiconductors are inspected, the connection resistance can be kept stable. Further, since the aluminum surface of the input / output terminal is not damaged by the inspection, the connection reliability of the semiconductor after the inspection is not deteriorated.

【0008】[0008]

【発明の実施の形態】以下、この発明の実施例について
図1乃至図4を用いて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

【0009】図1は本発明に係る半導体検査装置の第一
の実施例を示す断面図である。本発明に係る半導体検査
装置では、検査の前に半導体21の入出力端子22に突
起電極24を形成しておく。入出力端子22がアルミの
蒸着膜で形成されている場合は、サーモソニックボンデ
ィングを用いて、金ボールを入出力端子22の表面へ接
続することで突起電極24を形成する。
FIG. 1 is a sectional view showing a first embodiment of a semiconductor inspection apparatus according to the present invention. In the semiconductor inspection apparatus according to the present invention, the bump electrodes 24 are formed on the input / output terminals 22 of the semiconductor 21 before the inspection. When the input / output terminal 22 is formed of an aluminum vapor-deposited film, the protruding electrode 24 is formed by connecting a gold ball to the surface of the input / output terminal 22 using thermosonic bonding.

【0010】半導体21の下面には、各突起電極24と
接触できるように形成された配線パターン25と可撓性
の絶縁フィルム26が配置される。TAB(Tape-Autom
ated-Bonding)テープを用いれば、約35ミクロンの厚
さを有する銅箔のエッチングにより、配線パターンの幅
を約50ミクロン、配線間隔を約50ミクロンまで微細
化することができる。 TABテープの絶縁フィルム2
6の材料としては、50ミクロンまたは75ミクロンの
厚さのポリイミドが広く用いられている。
On the lower surface of the semiconductor 21, a wiring pattern 25 and a flexible insulating film 26, which are formed so as to be able to contact the respective protruding electrodes 24, are arranged. TAB (Tape-Autom
When an ated-bonding tape is used, the width of the wiring pattern can be reduced to about 50 microns and the wiring interval can be reduced to about 50 microns by etching a copper foil having a thickness of about 35 microns. TAB tape insulation film 2
As a material for No. 6, polyimide having a thickness of 50 microns or 75 microns is widely used.

【0011】図1では、フリップチップボンダ(図示せ
ず)の位置合わせ機能を用いて配線パターン25の位置
と半導体の突起電極24の位置を認識する。次いで、コ
レット27の吸着力Fにより半導体21を保持し、配線
パターン25と突起電極24が接触可能となる所定の位
置まで移動させた後、コレット27を下降させること
で、突起電極24と配線パターン25とを接触させる。
In FIG. 1, the position of the wiring pattern 25 and the position of the semiconductor protruding electrode 24 are recognized using the positioning function of a flip chip bonder (not shown). Next, the semiconductor 21 is held by the attraction force F of the collet 27, and is moved to a predetermined position where the wiring pattern 25 and the protruding electrode 24 can be brought into contact with each other. 25.

【0012】突起電極24はその形成方法により電極の
高さにばらつきが生じる。電極の形成方法として一般に
用いられている金ボールのサーモソニックボンディング
では、金ワイヤを引き千切った状態で、電極の高さは平
均90ミクロン、ばらつきは±20ミクロンに達する。
この高さばらつきを小さくする方法としては、平坦なツ
ールを押し当てて突起の先端部をつぶす工程が良く用い
られる。しかし、高さばらつきの低減には限界があり、
以上の工程を施しても±5ミクロン程度の高さばらつき
が残る。
The height of the protruding electrodes 24 varies depending on the method of forming them. In the thermosonic bonding of a gold ball, which is generally used as a method for forming an electrode, the height of the electrode reaches 90 μm on average and the dispersion reaches ± 20 μm when the gold wire is cut apart.
As a method of reducing the height variation, a step of pressing a flat tool to crush the tip of the projection is often used. However, there is a limit to the reduction of height variation,
Even if the above steps are performed, a height variation of about ± 5 μm remains.

【0013】以上の平坦化工程を施した突起電極24と
配線パターン25を接触させると、±5ミクロンの高さ
ばらつきを吸収するように配線パターン25と絶縁フィ
ルム26が弾性変形する。特に有機材料のポリイミドか
らなる絶縁フィルム26の変形量が大きく、厚さ50ミ
クロンまたは75ミクロンの厚さのポリイミドが弾性変
形する範囲内で、最大10ミクロンの高さばらつきを充
分吸収できる。この弾性変形により、全ての突起電極2
4と配線パターン25との電気的接続が確保され、半導
体21の機能を検査することができる。検査終了後、コ
レット27の吸着力Fにより半導体21を取り外せば、
弾性変形していた配線パターン25と絶縁フィルム26
は検査前の形状に復帰する。以上の操作を繰り返すこと
により、多数の半導体21に対して安定した電気的接続
による検査を実現できる。
When the wiring pattern 25 is brought into contact with the protruding electrode 24 subjected to the above-described flattening step, the wiring pattern 25 and the insulating film 26 are elastically deformed so as to absorb a height variation of ± 5 μm. In particular, as long as the amount of deformation of the insulating film 26 made of an organic polyimide material is large and the polyimide having a thickness of 50 μm or 75 μm is elastically deformed, a height variation of up to 10 μm can be sufficiently absorbed. Due to this elastic deformation, all the projecting electrodes 2
4 and the wiring pattern 25 are electrically connected, and the function of the semiconductor 21 can be inspected. After the inspection, if the semiconductor 21 is removed by the suction force F of the collet 27,
Elastically deformed wiring pattern 25 and insulating film 26
Returns to the shape before inspection. By repeating the above operation, it is possible to realize an inspection with a stable electrical connection to many semiconductors 21.

【0014】[0014]

【発明の効果】本発明の半導体検査装置によれば、半導
体の入出力端子に形成した突起電極を介して電気的検査
を行うので、入出力端子表面のアルミ蒸着膜は損傷を受
けることはなく、検査の前後において半導体の接続信頼
性が劣化することはない。
According to the semiconductor inspection apparatus of the present invention, the electrical inspection is performed through the protruding electrodes formed on the input / output terminals of the semiconductor, so that the aluminum deposited film on the surface of the input / output terminals is not damaged. In addition, the connection reliability of the semiconductor does not deteriorate before and after the inspection.

【0015】また、絶縁フィルムまたは配線パターンが
突起電極の高さのばらつきに応じて弾性変形する方式な
ので、検査終了後に絶縁フィルムと配線パターンは検査
前の形状に復帰する。従来例のようにアルミ酸化膜を破
る必要はないので、多数の半導体を検査しても接続抵抗
が上昇することはなく、検査条件を安定に保つことがで
きる。
Further, since the insulating film or the wiring pattern is elastically deformed in accordance with the variation in the height of the protruding electrodes, the insulating film and the wiring pattern return to the shapes before the inspection after the inspection. Since there is no need to break the aluminum oxide film as in the conventional example, even if a large number of semiconductors are inspected, the connection resistance does not increase and the inspection conditions can be kept stable.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体検査装置の実施例を示す断
面図である。
FIG. 1 is a sectional view showing an embodiment of a semiconductor inspection device according to the present invention.

【図2】従来の半導体検査装置の実施例を示す断面図で
ある。
FIG. 2 is a sectional view showing an example of a conventional semiconductor inspection device.

【符号の説明】[Explanation of symbols]

10…ベース、11…ピン、12…弾性体、13…後
板、14…スペーサ、15…ソケットコネクタ、16…
コンタクトシート、17…バンプ、18…フェンス、1
9…フタ、20…ネジ、21…半導体、22…入出力端
子、23…検査用基板、24…突起電極、25…配線パ
ターン、26…絶縁フィルム、27…吸着コレット。
DESCRIPTION OF SYMBOLS 10 ... Base, 11 ... Pin, 12 ... Elastic body, 13 ... Rear plate, 14 ... Spacer, 15 ... Socket connector, 16 ...
Contact sheet, 17… Bump, 18… Fence, 1
9: lid, 20: screw, 21: semiconductor, 22: input / output terminal, 23: inspection board, 24: protruding electrode, 25: wiring pattern, 26: insulating film, 27: suction collet.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体の入出力端子に形成された複数の突
起電極を介して電気信号を供給することで、半導体の検
査を行う半導体検査装置において、前記突起電極が配列
された領域を含むように配置された可撓性の絶縁フィル
ムと、前記絶縁フイルム上に形成され、前記突起電極と
接触可能な所定の配線パターンとを有し、前記突起電極
を前記配線パターンへ押し付ける際に、前記配線パター
ンまたは前記絶縁フィルムが前記突起電極の高さのばら
つきに応じて弾性変形することで電気的接続を保つこと
を特徴とする半導体検査装置。
In a semiconductor inspection apparatus for inspecting a semiconductor by supplying an electric signal through a plurality of protruding electrodes formed on input / output terminals of a semiconductor, the semiconductor inspection apparatus includes an area in which the protruding electrodes are arranged. A flexible insulating film disposed on the insulating film, and a predetermined wiring pattern formed on the insulating film and capable of contacting the protruding electrode. When the protruding electrode is pressed against the wiring pattern, the wiring A semiconductor inspection device, wherein an electrical connection is maintained by elastically deforming a pattern or the insulating film in accordance with a variation in the height of the bump electrode.
JP11016620A 1999-01-26 1999-01-26 Semiconductor inspecting device Pending JP2000214216A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11016620A JP2000214216A (en) 1999-01-26 1999-01-26 Semiconductor inspecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11016620A JP2000214216A (en) 1999-01-26 1999-01-26 Semiconductor inspecting device

Publications (1)

Publication Number Publication Date
JP2000214216A true JP2000214216A (en) 2000-08-04

Family

ID=11921394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11016620A Pending JP2000214216A (en) 1999-01-26 1999-01-26 Semiconductor inspecting device

Country Status (1)

Country Link
JP (1) JP2000214216A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7008254B2 (en) 2004-01-05 2006-03-07 Sumitomo Wiring Systems, Ltd. Connector
US7511375B2 (en) 2004-10-01 2009-03-31 Yamaichi Electronics Co., Ltd. Semiconductor device carrier unit and semiconductor socket provided therewith

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7008254B2 (en) 2004-01-05 2006-03-07 Sumitomo Wiring Systems, Ltd. Connector
US7511375B2 (en) 2004-10-01 2009-03-31 Yamaichi Electronics Co., Ltd. Semiconductor device carrier unit and semiconductor socket provided therewith

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