JP2000151079A - Fine pattern and method of forming via hole - Google Patents

Fine pattern and method of forming via hole

Info

Publication number
JP2000151079A
JP2000151079A JP10317087A JP31708798A JP2000151079A JP 2000151079 A JP2000151079 A JP 2000151079A JP 10317087 A JP10317087 A JP 10317087A JP 31708798 A JP31708798 A JP 31708798A JP 2000151079 A JP2000151079 A JP 2000151079A
Authority
JP
Japan
Prior art keywords
layer
plating
polyimide
metal thin
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10317087A
Other languages
Japanese (ja)
Inventor
Tomonori Matsuura
友紀 松浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP10317087A priority Critical patent/JP2000151079A/en
Publication of JP2000151079A publication Critical patent/JP2000151079A/en
Pending legal-status Critical Current

Links

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  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve adhesion between polyimide and a conductive layer without chemical modification to a surface layer by enhancing deposition accuracy of a conductive layer to a via hole and performingalkaline solution processing such as hydrazine or glow discharge without electroless copper plating, in a method of forming a multilayer printed wiring board using a two-layer printed wiring board. SOLUTION: A metal thin-film layer 3 is formed on a rough surface of a metal foil 2, this metal thin-film layer 3 surface is laminated on a polyimide layer 1 formed on a substrate, this metal foil 2 is removed, this metal thin-film layer 3 is patterned, the polyimide layer 1 is drilled to form a hole 4, a conductive layer 6 is formed on the drilled portion of the polyimide layer 1 and a patterning region by direct plating, and a pattern and via holes are formed by electro-plating.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、フレキシブルプリ
ント配線板の配線及びビアホールの形成に係わるもので
あり、特に接着剤を用いない2層フレキシブルプリント
配線基板を用いた多層フレキシブルプリント配線板の微
細配線及びビアホールの形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of wiring and via holes in a flexible printed wiring board, and more particularly to the fine wiring of a multilayer flexible printed wiring board using a two-layer flexible printed wiring board without using an adhesive. And a method of forming a via hole.

【0002】[0002]

【従来の技術】従来、フレキシブルプリント配線基板に
使用されている配線基板材料は銅/接着剤層/ポリイミ
ド層というようにエポキシ系等の接着剤を用いた3層配
線基板が一般的であった。しかしながら、近年の電子機
器の高密度化、高速化、多機能化に伴い、これらの要求
に対応でき、さらに、耐熱性、屈曲性、耐マイグレーシ
ョン性、ボンディング性の特性に優れる、接着剤層を含
まない銅/ポリイミド層の2層配線基板が注目されHD
D、FDD、TABなどに使用されるようになってい
る。
2. Description of the Related Art Conventionally, as a wiring board material used for a flexible printed wiring board, a three-layer wiring board using an epoxy-based adhesive such as copper / adhesive layer / polyimide layer has been generally used. . However, with the recent increase in density, speed, and multi-functionality of electronic devices, an adhesive layer that can meet these demands and has excellent heat resistance, flexibility, migration resistance, and bonding properties has been developed. Attention has been focused on a two-layer wiring board with a copper / polyimide layer not containing HD
D, FDD, TAB, etc.

【0003】2層配線基板は製造方法により大きく2種
類に分類することができる。一つは基材に銅箔を用い、
銅箔上にポリイミドの前駆体であるポリアミック酸を塗
布しイミド化するキャスティング法、接着剤に熱可塑性
のポリイミドを使用するポリイミド接着剤法であり、も
う一つは基材にポリイミドフィルムを用い、ポリイミド
フィルム上にスパッタリング、蒸着、無電解めっき等で
導通層となる金属薄膜を直接形成し、電気めっきで金属
層の厚付けを行うメタライジング法である。近年では、
このような2層配線基板を用いた方法でフレキシブルプ
リント配線板を多層に積層する多層フレキシブルプリン
ト配線板が開発されるようになってきている。
A two-layer wiring board can be roughly classified into two types according to a manufacturing method. One uses copper foil for the base material,
Casting method to apply and imidize polyamic acid, which is a precursor of polyimide on copper foil, is a polyimide adhesive method using thermoplastic polyimide as an adhesive, another is using a polyimide film as a base material, This is a metallizing method in which a metal thin film serving as a conductive layer is directly formed on a polyimide film by sputtering, vapor deposition, electroless plating, or the like, and the metal layer is thickened by electroplating. in recent years,
Multilayer flexible printed wiring boards in which flexible printed wiring boards are stacked in multiple layers by a method using such a two-layer wiring board have been developed.

【0004】キャスティング法、ポリイミド接着剤法に
よる2層配線基板を用いた多層フレキシブルプリント配
線板における配線及び層間の電気的接続の役割を果たす
ビアホールの形成は、ポリイミド層の孔開け加工を施し
た後、配線及びビアホール部分のポリイミド上に、無電
解めっき法で導通層を形成し、電気めっきにより厚付け
めっきをすることにより行った。また、今日では無電解
めっき法にかえダイレクトプレーティング法により行う
ケースがある。しかしながら、この方法では層間接続用
の厚付けめっきが基材である銅箔上にも形成され配線層
が厚くなるため、微細な配線を形成することが困難であ
った。
[0004] In a multilayer flexible printed wiring board using a two-layer wiring board by a casting method or a polyimide adhesive method, a via hole which plays a role of wiring and electrical connection between layers is formed after forming a hole in the polyimide layer. A conductive layer was formed by electroless plating on the wiring and via hole portions of the polyimide, and the resultant was plated by electroplating. Further, there is a case where the plating is performed by a direct plating method instead of the electroless plating method today. However, in this method, thick plating for interlayer connection is also formed on the copper foil as the base material, and the wiring layer becomes thick, so that it has been difficult to form fine wiring.

【0005】メタライジング法による2層配線基板を用
いた方法での多層フレキシブルプリント配線板では、上
述したキャスティング法、ポリイミド接着剤法による問
題は回避できるが、スパッタリングや蒸着によるビアホ
ール部分への金属薄膜の形成が困難であり、無電解めっ
き法で一般的に形成されている。そして無電解めっき法
により導通層となる金属薄膜を形成した後、電気めっき
を行い、エッチングすることにより配線を形成するか若
しくは配線形成用のレジストをパターニングしてから電
気めっきを行い配線を形成していた。
In the case of a multilayer flexible printed wiring board using a two-layer wiring board by a metallizing method, the above-mentioned problems caused by the casting method and the polyimide adhesive method can be avoided. Is difficult to form, and is generally formed by an electroless plating method. Then, after forming a metal thin film to be a conductive layer by electroless plating, electroplating is performed, and wiring is formed by etching, or a resist for wiring formation is patterned, and then electroplating is performed to form wiring. I was

【0006】[0006]

【発明が解決しようとする課題】しかしながら、ビアホ
ール部分への金属薄膜形成に無電解めっき法を用いる
と、無電解めっきの工程において水素ガスが発生してビ
アホール内にガスが溜まるため導通層の析出信頼性が悪
くなる。これは、ビアホール径が小径化するに従い顕著
になり、小径ビアホールには不利となる。そして、無電
解めっき法として一般的に用いられる無電解銅めっきに
はホルムアルデヒドが含まれており、めっき浴不安定
性、老化めっき液の廃液、排水処理等で作業環境の問題
が多く、コストが嵩んでしまう。また、ポリイミドフィ
ルム等のポリイミド層を粗化させ、アンカー効果により
ポリイミド層と導体層の密着力を向上させることが困難
であるため、ポリイミド層上に密着性に優れた導通層を
形成するためには、グロー放電処理、ヒドラジン等のア
ルカリ溶液処理をして表面層を化学的に改質させること
が必要となるためコストがかかり、さらに、これらの処
理を施しても2層配線基板は3層配線基板と同様の密着
力を得ることは困難であった。
However, when an electroless plating method is used to form a metal thin film on a via hole portion, hydrogen gas is generated in the electroless plating process and gas is accumulated in the via hole, so that a conductive layer is deposited. The reliability becomes worse. This becomes more remarkable as the via hole diameter becomes smaller, and is disadvantageous for small diameter via holes. The electroless copper plating generally used as the electroless plating method contains formaldehyde, and there are many problems in the working environment due to plating bath instability, waste liquid of aging plating solution, wastewater treatment, etc., and cost increases. Get out. In addition, since it is difficult to roughen a polyimide layer such as a polyimide film and to improve the adhesion between the polyimide layer and the conductor layer due to an anchor effect, it is necessary to form a conductive layer having excellent adhesion on the polyimide layer. It is necessary to chemically modify the surface layer by performing glow discharge treatment or treatment with an alkali solution such as hydrazine, so that the cost is high. It was difficult to obtain the same adhesion as a wiring board.

【0007】本発明は上記課題を解決したものであり、
無電解めっき法を用いないためビアホールへの導通層の
析出信頼性を高くすることができ、廃液処理負担が大幅
に削減されるため作業環境も良好となる。また、グロー
放電処理やヒドラジン等のアルカリ溶液処理を行ってポ
リイミド表面層を化学的に改質させなくても導通層とポ
リイミド層との密着力が良好であることから、信頼性の
高い微細配線及びビアホールを形成することができる
上、コストも削減することができるものである。
[0007] The present invention has solved the above problems,
Since the electroless plating method is not used, the reliability of deposition of the conductive layer in the via hole can be increased, and the work environment can be improved because the burden of waste liquid treatment is greatly reduced. In addition, since the adhesion between the conductive layer and the polyimide layer is good even if the polyimide surface layer is not chemically modified by performing a glow discharge treatment or an alkali solution treatment such as hydrazine, a highly reliable fine wiring In addition, a via hole can be formed, and the cost can be reduced.

【0008】[0008]

【課題を解決するための手段】微細配線及びビアホール
の形成方法において、金属箔の粗化処理された面に金属
薄膜層を形成して、該金属薄膜層面を基板上に形成した
ポリイミド層上に積層し、該金属箔をエッチングにより
除去した後、該金属薄膜層の一部をエッチングにより除
去し、前記金属薄膜層を用いて該ポリイミド層の孔開け
加工を行い、その後、金属薄膜層を電極端子用接点部分
を除きエッチングにより除去して、ポリイミド層の孔開
け加工部分と配線形成領域にダイレクトプレーティング
法を用いて導通層を形成し、その上に電気めっき法で厚
付けめっきを行うことにより、配線と、該ポリイミド層
の孔開け加工部分の層間接続と、を形成することを特徴
とするものである。
In a method for forming fine wiring and via holes, a metal thin film layer is formed on a roughened surface of a metal foil, and the metal thin film layer surface is formed on a polyimide layer formed on a substrate. After laminating and removing the metal foil by etching, a part of the metal thin film layer is removed by etching, and a hole is formed in the polyimide layer using the metal thin film layer. Except for the contact part for the terminal, remove by etching, form a conductive layer using the direct plating method on the drilled part of the polyimide layer and the wiring formation area, and then perform thick plating by electroplating on it Thus, a wiring and an interlayer connection in a perforated portion of the polyimide layer are formed.

【0009】[0009]

【発明の実施の形態】以下に図1を用いて、微細配線及
びビアホールの形成方法を説明する。図1に示す配線基
板材料は、基板として銅基板を、該基板上に配線の絶縁
層としてポリイミド層1を用いており、粗化処理された
金属箔2の粗化処理面に金属薄膜層3を形成し、該金属
薄膜層3面をポリイミド層1上に積層させている(図1
(a))。最初に配線及びビアホールを形成するための
加工部分上にあたる金属箔をエッチングにより除去した
後(図1(b))、金属薄膜層3をビアホール4形成用
のマスクとして用いるため一部エッチングにより除去し
(図1(c))、この金属薄膜層3をマスクとしてエッ
チングすることにより、ポリイミド層1にビアホール4
を形成した(図1(d))。その後、該配線基板材料の
金属薄膜層3は、後述するダイレクトプレーティングを
行う際の電極端子用接点5として残しておく部分を除い
てエッチングにより除去する(図1(e))。さらに、
露出したポリイミド層1、電極端子用接点5、ビアホー
ル4上に前処理を行った後、硫酸銅めっき液を用いて、
ダイレクトプレーティングにより銅めっき6を全面に形
成した(図1(f))。次に、ダイレクトプレーティン
グにて形成した銅めっき6上に、電気めっき法で銅めっ
きを形成するためのマスク用としてめっきレジスト7を
塗布・製版した(図1(g))。そして、電気めっき法
にて10μmの厚さとなるよう銅めっき配線を形成する
と同時にビアホール部分の銅めっき厚付けを行った後
(図1(h))、マスク用であるめっきレジスト7を剥
離し(図1(i))、これによって露出した銅めっき6
をソフトエッチング除去した(図1(j))。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming a fine wiring and a via hole will be described below with reference to FIG. The wiring board material shown in FIG. 1 uses a copper substrate as a substrate and a polyimide layer 1 as an insulating layer of wiring on the substrate. A metal thin film layer 3 is formed on a roughened surface of a roughened metal foil 2. Is formed, and the surface of the metal thin film layer 3 is laminated on the polyimide layer 1 (FIG. 1).
(A)). First, after the metal foil corresponding to the processed portion for forming the wiring and the via hole is removed by etching (FIG. 1B), the metal thin film layer 3 is partially removed by etching to be used as a mask for forming the via hole 4. (FIG. 1 (c)), the via hole 4 is formed in the polyimide layer 1 by etching using the metal thin film layer 3 as a mask.
Was formed (FIG. 1D). Thereafter, the metal thin film layer 3 of the wiring board material is removed by etching except for a portion to be left as an electrode terminal contact 5 when performing direct plating, which will be described later (FIG. 1E). further,
After performing a pretreatment on the exposed polyimide layer 1, the electrode terminal contact 5, and the via hole 4, using a copper sulfate plating solution,
Copper plating 6 was formed on the entire surface by direct plating (FIG. 1 (f)). Next, a plating resist 7 was applied and plate-formed on a copper plating 6 formed by direct plating as a mask for forming copper plating by an electroplating method (FIG. 1 (g)). Then, after forming a copper-plated wiring so as to have a thickness of 10 μm by an electroplating method and performing copper plating thickening of the via hole at the same time (FIG. 1H), the plating resist 7 for the mask is peeled off ( FIG. 1 (i)) The copper plating 6 exposed thereby.
Was removed by soft etching (FIG. 1 (j)).

【0010】[0010]

【実施例】次に図1に従って実施例について示します。
実施例の配線基板材料は金属箔、金属薄膜層、ポリイミ
ド層からなり、該金属箔2としては粗化処理された1/
2OZ(18μm)の銅箔を用い、金属箔2の粗化処理
面に該金属薄膜層3として電気めっき法により0.5μ
mの厚さでNiを形成し、金属薄膜層3面を該ポリイミ
ド層1上に積層させた(図1(a))。次に配線及びビ
アホールを形成するための加工部分(少なくとも配線形
成領域及びビアホール部分を含む)に積層された金属箔
2をアンモニア系アルカリエッチング液(メルテック製
エープロセス)を用いて除去する(図1(b))。この
後、金属薄膜層3上にドライフィルムレジスト(旭化成
工業(株)製のサンフォートAQ)をラミネートして、
該ドライフィルムレジストをパターニングした。このパ
ターニングされたドライフィルムレジストを用いて、ビ
アホール部分上の金属薄膜層3を過酸化水素―硫酸系の
エッチング液(奥野製薬工業製のトリップスRS―II)
を使用することにより除去した(図1(c))。この金
属薄膜層3をマスクとして用い、水酸化カリウムと脂肪
族アミンの混合物を主成分とするエッチング液(東レエ
ンジニアリング(株)製のTPE―3000)を使用し
てポリイミド層1にビアホール4の孔開け加工を行った
(図1(d))。さらに、パターニングされたドライフ
ィルムレジストを用いて、過酸化水素−硫酸系のエッチ
ング液(奥野製薬工業製のトリップスRS−II)を使用
し、金属薄膜層3を加工して電極端子用接点5を形成し
た(図1(e))。この後、露出したポリイミド層1、
電極端子用接点5、ビアホール4上にアトテック・ジャ
パン製のネオパクトプロセスを用いて、ダイレクトプレ
ーティングするための前処理を行った。表1にネオパク
トプロセスの概略及び条件を示す。ネオパクトプロセス
の後、硫酸銅めっき液を使用し、電極端子用接点5を用
いてダイレクトプレーティングにより銅めっき6を全面
に形成するが、銅めっき6の膜厚を極力薄く形成するた
めに、低電流密度の条件にて行った(図1(f))。表
2にこの時の硫酸銅めっき液組成とめっき条件を示す。
尚、添加剤としてはアトテック・ジャパン製のカパラシ
ドHLを用いた。この後、ダイレクトプレーティングに
て形成した銅めっき6上に電気めっき法により銅配線を
形成するためのマスクとして、めっきレジスト7(東京
応化工業製のPMER P−LA900 PM)を12
μmの厚さになるように塗布し、製版した(図1
(g))。そして、銅めっき6上に銅めっき配線が10
μmの厚さとなるように電気めっきにて銅配線を厚付け
すると同時にビアホール部分の銅めっき6上にも電気め
っき法にて銅めっきを厚付けした(図1(h))。この
時の銅めっきを電気めっき法にて厚付けするための条件
を表3に示す。但し、スルーカップAC−90Mは上村
工業製の添加剤である。そして、銅めっき配線を形成し
た後、マスク用のめっきレジスト7を剥離し(図1
(i))、これにより露出した銅めっき6をソフトエッ
チングにより除去した(図1(j))。
Next, an embodiment will be described with reference to FIG.
The wiring board material of the embodiment is composed of a metal foil, a metal thin film layer, and a polyimide layer.
Using a copper foil of 20 OZ (18 μm), the metal thin film layer 3 is formed on the roughened surface of the metal foil 2 by electroplating to a thickness of 0.5 μm.
Ni was formed to a thickness of m and the metal thin film layer 3 was laminated on the polyimide layer 1 (FIG. 1A). Next, the metal foil 2 laminated on the processed portion for forming the wiring and the via hole (including at least the wiring forming region and the via hole portion) is removed using an ammonia-based alkali etching solution (A process manufactured by Meltec) (FIG. 1). (B)). Thereafter, a dry film resist (Sunfort AQ manufactured by Asahi Kasei Corporation) is laminated on the metal thin film layer 3,
The dry film resist was patterned. Using this patterned dry film resist, the metal thin film layer 3 on the via hole portion is etched with a hydrogen peroxide-sulfuric acid type etching solution (trips RS-II manufactured by Okuno Pharmaceutical).
(FIG. 1 (c)). Using the metal thin film layer 3 as a mask, a via hole 4 is formed in the polyimide layer 1 by using an etching solution (TPE-3000 manufactured by Toray Engineering Co., Ltd.) mainly containing a mixture of potassium hydroxide and an aliphatic amine. Opening was performed (FIG. 1D). Further, using a patterned dry film resist, using a hydrogen peroxide-sulfuric acid type etching solution (trips RS-II manufactured by Okuno Pharmaceutical Co., Ltd.), the metal thin film layer 3 is processed, and the electrode terminal contact 5 is formed. It was formed (FIG. 1 (e)). After this, the exposed polyimide layer 1,
A pretreatment for direct plating was performed on the electrode terminal contact 5 and the via hole 4 using a Neopact process manufactured by Atotech Japan. Table 1 shows the outline and conditions of the neopact process. After the neopact process, a copper sulfate plating solution is used, and a copper plating 6 is formed on the entire surface by direct plating using the electrode terminal contacts 5, but in order to form the copper plating 6 as thin as possible, This was performed under the condition of low current density (FIG. 1 (f)). Table 2 shows the composition of the copper sulfate plating solution and the plating conditions at this time.
In addition, Captoside HL manufactured by Atotech Japan was used as an additive. Thereafter, a plating resist 7 (PMER P-LA900 PM manufactured by Tokyo Ohka Kogyo Co., Ltd.) was used as a mask for forming copper wiring by electroplating on the copper plating 6 formed by direct plating.
It was applied to a thickness of μm and made into a plate (Fig. 1
(G)). Then, when the copper plating wiring is 10
The copper wiring was thickened by electroplating so as to have a thickness of μm, and at the same time, the copper plating was also thickened on the copper plating 6 in the via hole portion by electroplating (FIG. 1 (h)). Table 3 shows the conditions for thickening the copper plating by the electroplating method at this time. However, the through cup AC-90M is an additive manufactured by Uemura Kogyo. Then, after forming the copper plating wiring, the plating resist 7 for the mask is peeled off (FIG. 1).
(I)) The exposed copper plating 6 was removed by soft etching (FIG. 1 (j)).

【0011】尚、実施例では、金属箔として粗化処理さ
れた銅箔を用いたが、これらに限定されるものでなく、
粗化処理された金属箔がエッチング除去できるものであ
ればよい。また、ポリイミド層のビアホール加工にウェ
ットエッチング法を用いたが、本発明はこの方法に限定
されるものではなく、レーザー加工、プラズマ加工、ブ
ラスト加工等、ポリイミド層が加工できる方法であれば
よい。
In the embodiment, the roughened copper foil is used as the metal foil. However, the metal foil is not limited thereto.
Any material can be used as long as the roughened metal foil can be removed by etching. In addition, although the wet etching method was used for the via hole processing of the polyimide layer, the present invention is not limited to this method, and any method capable of processing the polyimide layer such as laser processing, plasma processing, blast processing, or the like may be used.

【0012】[0012]

【表1】 [Table 1]

【0013】[0013]

【表2】 [Table 2]

【0014】[0014]

【表3】 [Table 3]

【0015】[0015]

【発明の効果】本発明によれば、配線基板の形成方法に
おいて、金属薄膜層の粗化処理された面をポリイミド層
上に積層し、該金属薄膜層にビアホール形成用マスクと
して用いるためのパターンを形成して該ポリイミド層の
孔開け加工を行い、該金属薄膜層を電極端子部分のみ残
し除去し、該ポリイミド層の孔開け加工部分と配線形成
領域にダイレクトプレーティング法により導通層を形成
し、電気めっき法にて配線及び層間接続用の厚付けめっ
きを形成することを特徴とすることにより、無電解めっ
きを用いなくてもビアホールへの導通層の形成が可能と
なった。この結果、小径ビアホールへの析出信頼性が高
くなり、廃液処理負担が大幅に削減でき、作業環境も良
好となる。また、粗化処理された金属薄膜層は、グロー
放電処理、ヒドラジン等のアルカリ溶液処理により表面
層を化学的に改質させなくてもポリイミド層と導通層と
の密着力を良好にすることが出来るため信頼性が高く、
低コスト化することができるものである。その上、電極
端子部分のみ金属薄膜層を残し、電極端子部分に相当す
る部位以外の金属薄膜層を除去するため、ビアホール部
分と配線形成領域にダイレクトプレーティングする際、
電極端子の接点焼け等が生じず、良好なダイレクトプレ
ーティングが可能となりプロセスが安定する上、当然金
属薄膜層は電極端子用接点にもなるものであるため製造
効率を促進させることができる。
According to the present invention, in a method of forming a wiring board, a roughened surface of a metal thin film layer is laminated on a polyimide layer, and a pattern for using the metal thin film layer as a mask for forming a via hole is formed. To form a hole in the polyimide layer, remove the metal thin film layer leaving only the electrode terminal portions, and form a conductive layer by a direct plating method in the hole-formed portion and the wiring formation region of the polyimide layer. By forming thick plating for wiring and interlayer connection by an electroplating method, a conductive layer can be formed in a via hole without using electroless plating. As a result, the reliability of deposition in the small-diameter via hole is increased, the burden of waste liquid treatment can be greatly reduced, and the working environment is improved. In addition, the roughened metal thin film layer can improve the adhesion between the polyimide layer and the conductive layer without chemically modifying the surface layer by glow discharge treatment or treatment with an alkali solution such as hydrazine. High reliability because it can be
The cost can be reduced. In addition, when leaving the metal thin film layer only in the electrode terminal portion and removing the metal thin film layer other than the portion corresponding to the electrode terminal portion, when directly plating the via hole portion and the wiring formation region,
Contact burning of the electrode terminals does not occur, good direct plating is possible, and the process is stabilized. In addition, since the metal thin film layer also serves as a contact for the electrode terminal, production efficiency can be promoted.

【図面の簡単な説明】[Brief description of the drawings]

【図1】微細配線及びビアホール形成方法を示す図であ
る。
FIG. 1 is a diagram showing a method for forming a fine wiring and a via hole.

【符号の説明】[Explanation of symbols]

1・・・・ポリイミド層 2・・・・金属箔 3・・・・金属薄膜層 4・・・・ビアホール 5・・・・電極端子用接点 6・・・・銅めっき 7・・・・めっきレジスト 1 ··· Polyimide layer 2 ··· Metal foil 3 ··· Metal thin film layer 4 ··· Via hole 5 ··· Contact for electrode terminal 6 ··· Copper plating 7 ··· Plating Resist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】微細配線及びビアホールの形成方法におい
て、金属箔の粗化処理された面に金属薄膜層を形成し
て、該金属薄膜層面を基板上に形成したポリイミド層上
に積層し、該金属箔をエッチングにより除去した後、該
金属薄膜層の一部をエッチングにより除去し、前記金属
薄膜層を用いて該ポリイミド層の孔開け加工を行い、そ
の後金属薄膜層を電極端子用接点部分を除きエッチング
により除去して、ポリイミド層の孔開け加工部分と配線
形成領域にダイレクトプレーティング法を用いて導通層
を形成し、その上に電気めっき法で厚付けめっきを行う
ことにより、配線と、ポリイミド層の孔開け加工部分の
層間接続と、を形成することを特徴とする微細配線及び
ビアホールの形成方法。
In a method of forming fine wiring and via holes, a metal thin film layer is formed on a roughened surface of a metal foil, and the metal thin film layer surface is laminated on a polyimide layer formed on a substrate. After the metal foil is removed by etching, a part of the metal thin film layer is removed by etching, and a hole is formed in the polyimide layer using the metal thin film layer. Removed by etching, forming a conductive layer using a direct plating method in the hole forming portion of the polyimide layer and the wiring forming area, and performing thick plating by electroplating on the conductive layer, Forming a via and a via hole in a portion of the polyimide layer where a hole is formed by punching.
JP10317087A 1998-11-09 1998-11-09 Fine pattern and method of forming via hole Pending JP2000151079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10317087A JP2000151079A (en) 1998-11-09 1998-11-09 Fine pattern and method of forming via hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10317087A JP2000151079A (en) 1998-11-09 1998-11-09 Fine pattern and method of forming via hole

Publications (1)

Publication Number Publication Date
JP2000151079A true JP2000151079A (en) 2000-05-30

Family

ID=18084293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10317087A Pending JP2000151079A (en) 1998-11-09 1998-11-09 Fine pattern and method of forming via hole

Country Status (1)

Country Link
JP (1) JP2000151079A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1335643A2 (en) * 2002-02-06 2003-08-13 Nitto Denko Corporation Method for manufacturing double-sided circuit board
US7855342B2 (en) 2000-09-25 2010-12-21 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US7884286B2 (en) 2000-02-25 2011-02-08 Ibiden Co., Ltd. Multilayer printed circuit board

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7884286B2 (en) 2000-02-25 2011-02-08 Ibiden Co., Ltd. Multilayer printed circuit board
US7888605B2 (en) 2000-02-25 2011-02-15 Ibiden Co., Ltd. Multilayer printed circuit board
US7888606B2 (en) 2000-02-25 2011-02-15 Ibiden Co., Ltd. Multilayer printed circuit board
US8438727B2 (en) 2000-02-25 2013-05-14 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US7855342B2 (en) 2000-09-25 2010-12-21 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US8293579B2 (en) 2000-09-25 2012-10-23 Ibiden Co., Ltd. Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
US8959756B2 (en) 2000-09-25 2015-02-24 Ibiden Co., Ltd. Method of manufacturing a printed circuit board having an embedded electronic component
US9245838B2 (en) 2000-09-25 2016-01-26 Ibiden Co., Ltd. Semiconductor element
EP1335643A2 (en) * 2002-02-06 2003-08-13 Nitto Denko Corporation Method for manufacturing double-sided circuit board
EP1335643A3 (en) * 2002-02-06 2005-01-19 Nitto Denko Corporation Method for manufacturing double-sided circuit board

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