JPH1022612A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH1022612A
JPH1022612A JP16898996A JP16898996A JPH1022612A JP H1022612 A JPH1022612 A JP H1022612A JP 16898996 A JP16898996 A JP 16898996A JP 16898996 A JP16898996 A JP 16898996A JP H1022612 A JPH1022612 A JP H1022612A
Authority
JP
Japan
Prior art keywords
conductive film
wiring board
printed wiring
coating film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16898996A
Other languages
Japanese (ja)
Other versions
JP2858564B2 (en
Inventor
Seiichi Inoue
誠一 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16898996A priority Critical patent/JP2858564B2/en
Publication of JPH1022612A publication Critical patent/JPH1022612A/en
Application granted granted Critical
Publication of JP2858564B2 publication Critical patent/JP2858564B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To omit the etching process of a conductive coating film, by eliminating the conductive coating film by eliminating the surface of a substratum under the conductive coating film except an electroplated part. SOLUTION: A conductive coating film 3 composed of a palladium sulfide coating film is formed on the surface of a substratum composed of insulator. Plating resist 4 is formed in a part except a desired conductive pattern. By electroplating, a conductor layer 5 is formed in a region except the part coated with the plating resist 4. The plating resist 4 is peeled off. The conductive coating film 3 in the part except the region where the conductor layer 5 is formed is eliminated. Since the conductive coating film 3 is thin and does not completely cover the surface of the substratum 1, the surface can be dissolved. By dissolving and eliminating the surface of the substratum 1, the conductive coating film 3 can be eliminated. Thereby the etching process of a conductive coating film which has been necessary in the conventional technique can be omitted.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【発明の属する技術分野】本発明は印刷配線板の製造方
法に関し、特に絶縁体からなる基材の表面にめっきによ
り導体層を形成する印刷配線板の製造方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board in which a conductive layer is formed on a surface of a substrate made of an insulator by plating.

【0001】[0001]

【従来の技術】絶縁体からなる基材の表面にめっきによ
り導体層を形成する方法には種々の方法がある。一般
に、導体層は、無電解めっきにより基材の表面に金属か
らなる薄い導電皮膜を形成した後、所望の厚みの電気め
っきを施すことにより形成される。また、無電解めっき
を用いずに導体層を形成する方法も報告されている。以
下に、特開昭57−49295に報告されている「導電
性パターンの形成方法」を従来技術として図3を参照し
ながら説明する。
2. Description of the Related Art There are various methods for forming a conductor layer on a surface of a base material made of an insulator by plating. In general, a conductive layer is formed by forming a thin conductive film made of a metal on the surface of a base material by electroless plating, and then performing electroplating with a desired thickness. Also, a method of forming a conductor layer without using electroless plating has been reported. Hereinafter, a "method of forming a conductive pattern" reported in JP-A-57-49295 will be described as a conventional technique with reference to FIG.

【0002】絶縁体からなる基材13の表面に、図3
(b)のごとく、接着剤14を塗布する。次いで、図3
(c)のごとく、真空あるいは不活性ガス雰囲気中で接
着剤14上に銅の溶融粒子を吹きつけ、銅からなる導電
皮膜15を形成する。次に、図3(d)のごとく、必要
な回路部分を除く部分上にめっきレジスト16を形成
し、図3(e)のごとく、電気めっきにより導体層17
を得る。次いで、図3(f)のごとく、めっきレジスト
16を剥離し、導電皮膜15をエッチング処理により除
去することにより、所望の導電性パターンを得る。
FIG. 3 shows a surface of a base material 13 made of an insulator.
As shown in (b), the adhesive 14 is applied. Then, FIG.
As shown in (c), molten copper particles are sprayed onto the adhesive 14 in a vacuum or an inert gas atmosphere to form a conductive film 15 made of copper. Next, as shown in FIG. 3 (d), a plating resist 16 is formed on portions excluding necessary circuit portions, and as shown in FIG. 3 (e), the conductor layer 17 is formed by electroplating.
Get. Next, as shown in FIG. 3 (f), the plating resist 16 is peeled off, and the conductive film 15 is removed by etching to obtain a desired conductive pattern.

【0003】[0003]

【発明が解決しようとする課題】上述のような従来技術
においては、以下のような課題がある。
The above-mentioned prior art has the following problems.

【0004】導電皮膜15を除去する為に必ずエッチン
グ処理を行わねばならない。エッチング処理は、塩化第
二銅、塩化第二鉄、過硫酸塩類、過酸化水素と硫酸、ア
ンモニアと塩酸等の水溶液が用いられるが、いずれの場
合も薬液の費用が高く、またエッチング処理廃液を環境
に影響を与えないように処理する場合にも高い費用が掛
かる。安価な印刷配線板を提供する上では無視できない
課題となる。同様に、無電解めっきによって金属からな
る導電皮膜を形成した場合もエッチングが必要となり、
安価な印刷配線板を提供する上では課題となる。
In order to remove the conductive film 15, an etching process must be performed. For the etching treatment, an aqueous solution of cupric chloride, ferric chloride, persulfates, hydrogen peroxide and sulfuric acid, ammonia and hydrochloric acid, etc. is used. High costs are also incurred when treating without affecting the environment. This is a problem that cannot be ignored in providing an inexpensive printed wiring board. Similarly, when a conductive film made of metal is formed by electroless plating, etching is necessary,
This is a problem in providing an inexpensive printed wiring board.

【0005】また、従来技術においては、導体層17の
下には常に接着剤14が存在するためスルーホール壁や
ビアホールの底で他の導体層と接続することができな
い。その為、片面または両面の印刷配線板には適用する
ことができるが、多層の印刷配線板には適用することが
できない。
In the prior art, since the adhesive 14 always exists under the conductor layer 17, it cannot be connected to another conductor layer at the through hole wall or the bottom of the via hole. Therefore, it can be applied to a single-sided or double-sided printed wiring board, but cannot be applied to a multilayer printed wiring board.

【0006】本発明は、かかる従来技術の欠点を解決し
た印刷配線板の製造方法を提供する。
[0006] The present invention provides a method for manufacturing a printed wiring board which overcomes the disadvantages of the prior art.

【0007】[0007]

【課題を解決するための手段】本発明は、絶縁体からな
る基材の表面に導電被膜を形成する工程と、必要な回路
部分を除く部分上にめっき用のレジストを形成する工程
と、必要な回路部分のみに電気めっきにより回路を形成
する工程と、めっき用のレジストを剥離する工程と、電
気めっきを施された部分以外の導電被膜の下の基材の表
層を除去することにより導電被膜を除去する工程を含む
ことを特徴とする印刷配線板の製造方法を提供する。
SUMMARY OF THE INVENTION The present invention comprises a step of forming a conductive film on the surface of a base material made of an insulator, a step of forming a resist for plating on portions except for necessary circuit portions, and Forming a circuit by electroplating only on the circuit portion, stripping the resist for plating, and removing the surface layer of the base material under the conductive film other than the portion subjected to electroplating to form the conductive film. And a method for manufacturing a printed wiring board, the method including:

【0008】[0008]

【発明の実施の形態】第一の実施形態例を図1を参照し
ながら説明する。印刷配線板の表面に所望のパターンの
回路を得ると共にスルーホールにめっき被膜を形成す
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described with reference to FIG. A circuit having a desired pattern is obtained on the surface of the printed wiring board, and a plating film is formed on the through holes.

【0009】(1)まず図1(a)に示すごとく、エポ
キシ、イミド等の絶縁体からなる基材1にドリルまたは
レーザー等の既知の方法を用いてスルーホール2を形成
する。スルーホール2の穴壁に内層接続が有る場合は、
ドリルによって発生したスミアやレーザーによって発生
した残渣を除去するために過マンガン酸処理を行う。
(2)次に、図1(b)に示すごとく、基材1の表面に
導電皮膜3を形成する。今回は導電皮膜3として、シプ
レイ社が提供する「クリムソンプロセス」(特開昭64
−65292、特開平1−268896)を用いた。表
1にプロセスの処理条件を示す。まず、センシタイザー
処理を行う。センシタイザー処理液はアルカリ性界面活
性剤とアミン類を含み、基材表面を清浄にすると共に、
後工程のアクチベーター処理での錫−パラジウムコロイ
ドの付き回りを改善する。
(1) First, as shown in FIG. 1A, a through hole 2 is formed in a base material 1 made of an insulator such as epoxy or imide by using a known method such as a drill or a laser. If there is an inner layer connection on the hole wall of through hole 2,
A permanganate treatment is performed to remove smears generated by the drill and residues generated by the laser.
(2) Next, as shown in FIG. 1B, a conductive film 3 is formed on the surface of the substrate 1. This time, as the conductive film 3, "Crimson Process" provided by Shipley (Japanese Patent Laid-Open No.
-65292, JP-A-1-268896). Table 1 shows the processing conditions of the process. First, a sensitizer process is performed. The sensitizer treatment solution contains an alkaline surfactant and amines, and cleans the substrate surface,
Improve the turn of the tin-palladium colloid in the post-activator treatment.

【0010】次にプレアクチベーター処理を行う。プレ
アクチベーター処理液はアクチベーター処理液と同じ媒
質からなり錫−パラジウムコロイドを含まない。主成分
として塩化ナトリウムを含み、次工程のアクチベーター
処理のpHおよび塩化物濃度が水洗水の持ち込みにより
変化することを防止する。
Next, a pre-activator process is performed. The pre-activator treatment solution is composed of the same medium as the activator treatment solution and does not contain a tin-palladium colloid. It contains sodium chloride as a main component and prevents the pH and chloride concentration of the activator treatment in the next step from being changed by the washing water.

【0011】次にアクチベーター処理を行う。アクチベ
ーター処理液は錫−パラジウムコロイドを含み、基材1
の表面に錫−パラジウムコロイドを吸着させる。
Next, an activator process is performed. The activator treatment solution contains a tin-palladium colloid, and the substrate 1
A tin-palladium colloid is adsorbed on the surface of.

【0012】次にコンバーター処理を行う。コンバータ
ー処理液は硼弗化水素酸を含み、基材1の表面に吸着し
た錫−パラジウムコロイドから錫の一部を除去し、主と
してパラジウムからなる皮膜を形成する。
Next, converter processing is performed. The converter treatment liquid contains borohydrofluoric acid and removes a part of tin from the tin-palladium colloid adsorbed on the surface of the substrate 1 to form a film mainly composed of palladium.

【0013】次に、エンハンサー処理を行う。エンハン
サー処理液はアルカリ金属の硫化物を含み、基材1の表
面に吸着したパラジウム皮膜を硫化パラジウム皮膜にす
る。
Next, an enhancer process is performed. The enhancer treatment solution contains an alkali metal sulfide, and turns the palladium film adsorbed on the surface of the substrate 1 into a palladium sulfide film.

【0014】次に、スタビライザー処理を行う。スタビ
ライザー処理液は水酸化ナトリウムを含み、基材1の表
面に吸着した硫化パラジウム皮膜を安定化させる。
Next, a stabilizer process is performed. The stabilizer treatment liquid contains sodium hydroxide and stabilizes the palladium sulfide film adsorbed on the surface of the substrate 1.

【0015】次にマイクロエッチング処理を行う。マイ
クロエッチング処理液は硫酸および過酸化水素を含み、
露出した銅の表面に形成された硫化パラジウム皮膜を除
去する。マイクロエッチング処理は、これ以降の工程
(4)により形成する導体層5がスルーホール壁やビア
ホールの底で他の層と接続する場合には必要である。接
続がない場合は行う必要は無い。
Next, a micro etching process is performed. The microetching solution contains sulfuric acid and hydrogen peroxide,
The palladium sulfide film formed on the exposed copper surface is removed. The micro-etching process is necessary when the conductor layer 5 formed in the subsequent step (4) is connected to another layer at the bottom of a through hole wall or a via hole. If there is no connection, there is no need to do this.

【0016】以上の処理により、絶縁体からなる基材1
の表面に硫化パラジウム皮膜からなる導電皮膜3が数百
オングストロームの厚みで形成される。近年、このよう
な導電皮膜の形成プロセスが多数考案され提供されてい
る。「クリムソンプロセス」以外にも、パラジウム皮膜
を形成するアトテック社の「ネオパクトプロセス」、リ
ーロナール社の「コンダクトロンDPプロセス」、カー
ボン皮膜を形成するマクダミッド社の「ブラックホール
プロセス」、荏原電算社の「シャドウプロセス」、ポリ
ピロール皮膜を形成するLPW社の「DMS−2プロセ
ス」等のプロセスが適用可能である。
By the above processing, the substrate 1 made of an insulator
A conductive film 3 made of a palladium sulfide film is formed on the surface of the substrate with a thickness of several hundred angstroms. In recent years, many processes for forming such a conductive film have been devised and provided. In addition to the Crimson Process, Atotech's Neopact Process, which forms a palladium film, Conducton DP Process, which is formed by Lilonal, MacDamid's Black Hole Process, which forms a carbon film, and Ebara Densan Co., Ltd. Processes such as a "shadow process" and a "DMS-2 process" of LPW which forms a polypyrrole film can be applied.

【0017】(3)次に、図1(c)に示すごとく、所
望の導体パターン以外の部分にめっきレジスト4を形成
する。通常めっきレジスト4は前処理・ドライフィルム
のラミネート・露光・現像の工程を経て形成される。前
処理にはソフトエッチングとして40g/Lの過酸化水
素と200g/Lの硫酸の溶液を使用し30秒間処理し
た。現像には10g/Lの炭酸ナトリウム溶液を使用し
3分間処理した。
(3) Next, as shown in FIG. 1C, a plating resist 4 is formed on portions other than the desired conductor pattern. Usually, the plating resist 4 is formed through the steps of pretreatment, lamination of a dry film, exposure and development. In the pre-treatment, a solution of 40 g / L of hydrogen peroxide and 200 g / L of sulfuric acid was used for soft etching for 30 seconds. The development was performed using a 10 g / L sodium carbonate solution for 3 minutes.

【0018】(4)次に図1(d)に示すごとく、めっ
きレジスト4で覆われた部分以外に電気めっきにより所
望の厚みの導体層5を形成する。導体層5の厚みは印刷
配線板の信頼性を大きく左右する。通常20μmから3
0μmの厚みを持つ場合が多い。前処理として、脱脂、
ソフトエッチングを行った。ソフトエッチングは40g
/Lの過酸化水素と200g/Lの硫酸の溶液を使用し
30秒間処理した。めっき液には硫酸銅めっき液を用い
た。80g/Lの硫酸銅、200g/Lの硫酸、50p
pmの塩酸に若干量の光沢剤を加えためっき液に45分
間浸漬し、2.5A/dm2の電流密度で電解すること
により、平均25μmの導体層5を得た。
(4) Next, as shown in FIG. 1D, a conductor layer 5 having a desired thickness is formed by electroplating on a portion other than the portion covered with the plating resist 4. The thickness of the conductor layer 5 greatly affects the reliability of the printed wiring board. Usually 20 μm to 3
It often has a thickness of 0 μm. As pretreatment, degreasing,
Soft etching was performed. 40g soft etching
/ L hydrogen peroxide and 200 g / L sulfuric acid solution for 30 seconds. A copper sulfate plating solution was used as the plating solution. 80 g / L copper sulfate, 200 g / L sulfuric acid, 50 p
The conductor layer 5 was immersed in a plating solution in which a slight amount of brightener was added to pm hydrochloric acid for 45 minutes, and electrolyzed at a current density of 2.5 A / dm2 to obtain a conductor layer 5 having an average of 25 μm.

【0019】(5)次に図1(e)に示すごとく、めっ
きレジスト4を剥離する。剥離には30g/Lの水酸化
ナトリウム溶液を使用し3分間処理した。
(5) Next, as shown in FIG. 1E, the plating resist 4 is peeled off. The peeling was performed using a 30 g / L sodium hydroxide solution for 3 minutes.

【0020】(6)次に図1(f)に示すごとく、導体
層5が形成された部分以外の導電被膜3を除去する。導
電皮膜3は化学吸着により基材1の表面に強固に密着し
ており、化学的にも安定で導電皮膜3自体を溶解または
分解して除去することは困難である。しかしながら、導
電皮膜3は薄く基材1の表面を完全に被覆してはいない
ので、基材1の表面を溶解することができる。したがっ
て、基材1の表面を溶解除去することにより導電被膜3
を除去することができる。基材1の溶解除去には過マン
ガン酸処理を使用した。濃硫酸処理等の適用も可能であ
る。本実施形態例でも工程(1)で行ったように、印刷
配線板の製造上、過マンガン酸処理はスミアの除去に広
く適用されている。表2に過マンガン酸処理の処理条件
を示す。導電被膜3を除去する場合は、工程(1)で行
ったように穴あけ後にスミアを除去する場合と比較し
て、約2倍の時間浸漬して基材1の溶解量を向上させて
いる。基材1の表面を平均約3μm溶解することで導電
被膜3は完全に除去することができる。このようにし
て、導電皮膜3を除去することにより、従来技術で必要
であった導電皮膜15のエッチング処理を省略すること
ができる。
(6) Next, as shown in FIG. 1F, the conductive coating 3 other than the portion where the conductor layer 5 is formed is removed. The conductive film 3 is firmly adhered to the surface of the substrate 1 by chemical adsorption, is chemically stable, and it is difficult to dissolve or decompose the conductive film 3 itself and remove it. However, since the conductive film 3 is thin and does not completely cover the surface of the substrate 1, the surface of the substrate 1 can be dissolved. Therefore, by dissolving and removing the surface of the substrate 1, the conductive coating 3
Can be removed. For dissolving and removing the substrate 1, a permanganate treatment was used. Application of concentrated sulfuric acid treatment or the like is also possible. In this embodiment, as in the step (1), the permanganate treatment is widely applied to the removal of smear in the production of a printed wiring board. Table 2 shows the processing conditions of the permanganate treatment. When the conductive film 3 is removed, the amount of the base material 1 dissolved is improved by immersion for about twice as long as when smear is removed after drilling as performed in the step (1). The conductive film 3 can be completely removed by dissolving the surface of the base material 1 on average by about 3 μm. By removing the conductive film 3 in this manner, the etching process of the conductive film 15 required in the related art can be omitted.

【0021】以上の工程を経て、基材1の表面およびス
ルーホール8の内壁に所望のパターンの導体層5を形成
する。
Through the above steps, the conductor layer 5 having a desired pattern is formed on the surface of the substrate 1 and the inner wall of the through hole 8.

【0022】第二の実施形態例を図2を参照しながら説
明する。導体層と絶縁層を順に形成し所望の層数を重ね
るビルドアップ工法において、絶縁層表面に所望のパタ
ーンの回路を形成すると共にビアホールにめっき被膜を
形成する。
A second embodiment will be described with reference to FIG. In a build-up method in which a conductor layer and an insulating layer are sequentially formed and a desired number of layers are stacked, a circuit having a desired pattern is formed on the surface of the insulating layer, and a plating film is formed in a via hole.

【0023】(1)まず図2(a)に示すごとく、エポ
キシ、イミド等の絶縁層6にレーザー等を用いてビアホ
ール8を形成する。絶縁層6に感光性樹脂を用い、フォ
トリソグラフィー法によりビアホール8を形成する方法
もある。
(1) First, as shown in FIG. 2A, a via hole 8 is formed in an insulating layer 6 of epoxy, imide or the like by using a laser or the like. There is also a method of forming a via hole 8 by photolithography using a photosensitive resin for the insulating layer 6.

【0024】(2)次に、図2(b)に示すごとく、絶
縁層6の表面に導電皮膜9を形成する。導電皮膜9とし
て、例えばシプレイ社が提供する「クリムソンプロセ
ス」を用いて、硫化パラジウム皮膜を数100オングス
トローム程度の厚みで形成する。表1にプロセスの処理
条件を示す。
(2) Next, as shown in FIG. 2B, a conductive film 9 is formed on the surface of the insulating layer 6. As the conductive film 9, a palladium sulfide film having a thickness of about several hundred angstroms is formed by using, for example, “Crimson process” provided by Shipley. Table 1 shows the processing conditions of the process.

【0025】[0025]

【表1】 [Table 1]

【0026】(3)次に、図2(c)に示すごとく、所
望の導体パターン以外の部分にめっきレジスト10を形
成する。通常めっきレジスト10は前処理・ドライフィ
ルムのラミネート・露光・現像の工程を経て形成され
る。前処理にはソフトエッチングとして40g/Lの過
酸化水素と200g/Lの硫酸の溶液を使用し30秒間
処理した。現像には10g/Lの炭酸ナトリウム溶液を
使用し3分間処理した。(4)次に図2(d)に示すご
とく、めっきレジスト10で覆われた部分以外に電気め
っきにより所望の厚みの導体層11を形成する。導体層
11の厚みは印刷配線板の信頼性を大きく左右する。通
常20μmから30μmの厚みを持つ場合が多い。前処
理として、脱脂、ソフトエッチングを行った。ソフトエ
ッチングは40g/Lの過酸化水素と200g/Lの硫
酸の溶液を使用し30秒間処理した。めっき液には硫酸
銅めっき液を用いた。80g/Lの硫酸銅、200g/
Lの硫酸、50ppmの塩酸に若干量の光沢剤を加えた
めっき液に45分間浸漬し、2.5A/dm2の電流密
度で電解することにより、平均25μmの導体層11を
得た。
(3) Next, as shown in FIG. 2C, a plating resist 10 is formed on portions other than the desired conductor pattern. Usually, the plating resist 10 is formed through steps of pretreatment, lamination of a dry film, exposure, and development. In the pre-treatment, a solution of 40 g / L of hydrogen peroxide and 200 g / L of sulfuric acid was used for soft etching for 30 seconds. The development was performed using a 10 g / L sodium carbonate solution for 3 minutes. (4) Next, as shown in FIG. 2D, a conductor layer 11 having a desired thickness is formed by electroplating on a portion other than the portion covered with the plating resist 10. The thickness of the conductor layer 11 greatly affects the reliability of the printed wiring board. Usually, it often has a thickness of 20 μm to 30 μm. As pretreatment, degreasing and soft etching were performed. Soft etching was performed for 30 seconds using a solution of 40 g / L hydrogen peroxide and 200 g / L sulfuric acid. A copper sulfate plating solution was used as the plating solution. 80 g / L copper sulfate, 200 g / L
The conductive layer 11 was immersed in a plating solution obtained by adding a slight amount of brightener to sulfuric acid of 50 L and 50 ppm of hydrochloric acid for 45 minutes, and electrolyzed at a current density of 2.5 A / dm 2, thereby obtaining a conductor layer 11 having an average of 25 μm.

【0027】(5)次に図2(e)に示すごとく、めっ
きレジスト10を剥離する。剥離には30g/Lの水酸
化ナトリウム溶液を使用し3分間処理した。
(5) Next, as shown in FIG. 2E, the plating resist 10 is peeled off. The peeling was performed using a 30 g / L sodium hydroxide solution for 3 minutes.

【0028】(6)次に図2(f)に示すごとく、導体
層11が形成された部分以外の導電被膜9を除去する。
導電皮膜9は薄く絶縁層6の表面を完全に被覆してはい
ないので、絶縁層6の表面を溶解することにより、絶縁
層6上に形成された導電被膜9を除去することができ
る。除去には過マンガン酸処理を使用した。表2に過マ
ンガン酸処理の処理条件を示す。
(6) Next, as shown in FIG. 2F, the conductive coating 9 other than the portion where the conductor layer 11 is formed is removed.
Since the conductive film 9 is thin and does not completely cover the surface of the insulating layer 6, the conductive film 9 formed on the insulating layer 6 can be removed by dissolving the surface of the insulating layer 6. Permanganate treatment was used for removal. Table 2 shows the processing conditions of the permanganate treatment.

【0029】[0029]

【表2】 [Table 2]

【0030】このようにして、導電皮膜9を除去するこ
とにより、従来技術で必要であった導電皮膜15のエッ
チング処理を省略することができる。
By removing the conductive film 9 in this manner, the etching of the conductive film 15 required in the prior art can be omitted.

【0031】以上の工程により、絶縁層6の表面および
ビアホール8の内壁に所望のパターンの導体層11を形
成すると共に、導体層11と導体層7を接続する。
Through the above steps, the conductor layer 11 having a desired pattern is formed on the surface of the insulating layer 6 and the inner wall of the via hole 8, and the conductor layer 11 and the conductor layer 7 are connected.

【0032】[0032]

【発明の効果】以上、本発明は、従来技術の製造方法に
おいて必要であった導電皮膜15のエッチング処理を省
略することで、安価な印刷配線板を得る製造方法を提供
する。
As described above, the present invention provides a manufacturing method for obtaining an inexpensive printed wiring board by omitting the etching treatment of the conductive film 15 which is required in the conventional manufacturing method.

【0033】また、片面または両面の印刷配線板だけで
はなく、多層の印刷配線板にも適用することのできる印
刷配線板の製造方法を提供する。
Further, the present invention provides a method for manufacturing a printed wiring board which can be applied not only to a single-sided or double-sided printed wiring board but also to a multilayer printed wiring board.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の工法を示す断面図。FIG. 1 is a sectional view showing a method of the present invention.

【図2】本発明の工法を示す断面図。FIG. 2 is a cross-sectional view showing the method of the present invention.

【図3】従来工法を示す断面図。FIG. 3 is a sectional view showing a conventional method.

【符号の説明】[Explanation of symbols]

1 基材 2 スルーホール 3 導電被膜 4 めっきレジスト 5 導体層 6 絶縁層 7 導体層 8 ビアホール 9 導電被膜 10 めっきレジスト 11 導体層 12 基材 13 スルーホール 14 接着剤 15 導電皮膜 16 めっきレジスト 17 導体層 DESCRIPTION OF SYMBOLS 1 Base material 2 Through hole 3 Conductive film 4 Plating resist 5 Conductive layer 6 Insulating layer 7 Conductive layer 8 Via hole 9 Conductive film 10 Plating resist 11 Conductive layer 12 Base material 13 Through hole 14 Adhesive 15 Conductive film 16 Plating resist 17 Conductive layer

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 絶縁体からなる基材の表面に導電被膜を
形成する工程と、必要な回路部分を除く部分上にめっき
用のレジストを形成する工程と、必要な回路部分のみに
電気めっきにより回路を形成する工程と、めっき用のレ
ジストを剥離する工程と、電気めっきを施された部分以
外の導電被膜の下の基材の表面を除去することにより導
電被膜を除去する工程を含むことを特徴とする印刷配線
板の製造方法。
1. A step of forming a conductive film on a surface of a base material made of an insulator, a step of forming a plating resist on portions excluding required circuit portions, and electroplating only required circuit portions. Forming a circuit, removing the resist for plating, and removing the conductive film by removing the surface of the substrate under the conductive film other than the electroplated portion. A method for manufacturing a printed wiring board, which is characterized by the following.
【請求項2】 前記導電被膜として硫化パラジウム皮膜
を基材の表面に形成することを特徴とする請求項1記載
の印刷配線板の製造方法。
2. The method for manufacturing a printed wiring board according to claim 1, wherein a palladium sulfide film is formed on the surface of the substrate as the conductive film.
【請求項3】 前記導電被膜としてパラジウム皮膜を基
材の表面に形成することを特徴とする請求項1記載の印
刷配線板の製造方法。
3. The method for manufacturing a printed wiring board according to claim 1, wherein a palladium film is formed on the surface of the substrate as the conductive film.
【請求項4】 前記導電被膜としてカーボン皮膜を基材
の表面に形成することを特徴とする請求項1記載の印刷
配線板の製造方法。
4. The method according to claim 1, wherein a carbon film is formed on the surface of the substrate as the conductive film.
【請求項5】 前記導電被膜としてポリピロール皮膜を
基材の表面に形成することを特徴とする請求項1記載の
印刷配線板の製造方法。
5. The method for producing a printed wiring board according to claim 1, wherein a polypyrrole film is formed on the surface of the substrate as the conductive film.
【請求項6】 前記電気めっきを施された部分以外の導
電被膜の下の基材の表層を除去することにより導電被膜
を除去する工程が過マンガン酸処理であることを特徴と
する請求項1記載の印刷配線板の製造方法。
6. The method according to claim 1, wherein the step of removing the conductive film by removing a surface layer of the base material under the conductive film other than the electroplated portion is permanganate treatment. The method for producing a printed wiring board according to the above.
【請求項7】 前記電気めっきを施された部分以外の導
電被膜の下の基材の表層を除去することにより導電被膜
を除去する工程が濃硫酸処理であることを特徴とする請
求項1記載の印刷配線板の製造方法。
7. The method according to claim 1, wherein the step of removing the conductive film by removing a surface layer of the base material under the conductive film other than the electroplated portion is a concentrated sulfuric acid treatment. Manufacturing method of printed wiring board.
JP16898996A 1996-06-28 1996-06-28 Manufacturing method of printed wiring board Expired - Fee Related JP2858564B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16898996A JP2858564B2 (en) 1996-06-28 1996-06-28 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16898996A JP2858564B2 (en) 1996-06-28 1996-06-28 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH1022612A true JPH1022612A (en) 1998-01-23
JP2858564B2 JP2858564B2 (en) 1999-02-17

Family

ID=15878296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16898996A Expired - Fee Related JP2858564B2 (en) 1996-06-28 1996-06-28 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP2858564B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100401821B1 (en) * 2001-12-12 2003-10-17 주식회사 쎄라닉스 the thin film circuit formation method which uses a metal chemical compound reaction
JP2013149871A (en) * 2012-01-20 2013-08-01 Asahi Kasei E-Materials Corp Flexible wiring board
JP2013149870A (en) * 2012-01-20 2013-08-01 Asahi Kasei E-Materials Corp Multilayer flexible wiring board and method for manufacturing multilayer flexible wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100401821B1 (en) * 2001-12-12 2003-10-17 주식회사 쎄라닉스 the thin film circuit formation method which uses a metal chemical compound reaction
JP2013149871A (en) * 2012-01-20 2013-08-01 Asahi Kasei E-Materials Corp Flexible wiring board
JP2013149870A (en) * 2012-01-20 2013-08-01 Asahi Kasei E-Materials Corp Multilayer flexible wiring board and method for manufacturing multilayer flexible wiring board

Also Published As

Publication number Publication date
JP2858564B2 (en) 1999-02-17

Similar Documents

Publication Publication Date Title
JP3594894B2 (en) Via filling plating method
KR20060114010A (en) Method of electroplating on aluminum
US5302492A (en) Method of manufacturing printing circuit boards
US20060070769A1 (en) Printed circuit board and method of fabricating same
US20050241954A1 (en) Electrolytic gold plating method of printed circuit board
JP2003008199A (en) Method for roughening copper surface of printed wiring board and printed wiring board and its producing method
JP4155434B2 (en) Manufacturing method of semiconductor package substrate having pads subjected to partial electrolytic plating treatment
JPH1065315A (en) Manufacturing method of a flexible printed circuit and a flexible printed circuit obtained in same method
JP4129665B2 (en) Manufacturing method of substrate for semiconductor package
US6544584B1 (en) Process for removal of undesirable conductive material on a circuitized substrate and resultant circuitized substrate
JP2858564B2 (en) Manufacturing method of printed wiring board
US4976808A (en) Process for removing a polyimide resin by dissolution
EP0402811B1 (en) Method of manufacturing printed circuit boards
US4968398A (en) Process for the electrolytic removal of polyimide resins
JPH05259611A (en) Production of printed wiring board
KR101555014B1 (en) Printed circuit board for forming fine wiring and method for manufacturing the same
EP0476065A1 (en) Method for improving the insulation resistance of printed circuits.
US4874635A (en) Method for removing residual precious metal catalyst from the surface of metal-plated plastics
JP2003204138A (en) Manufacturing method for printed wiring board
JPH08148810A (en) Manufacture of printed wiring board
JP2624068B2 (en) Manufacturing method of printed wiring board
JP3951938B2 (en) Etching method and printed wiring board manufacturing method using the same
JP4555998B2 (en) Printed wiring board
JPH0710028B2 (en) Printed board manufacturing method
JPH08139435A (en) Manufacture of printed wiring board

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19981104

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071204

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081204

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091204

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091204

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101204

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101204

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111204

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121204

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131204

Year of fee payment: 15

LAPS Cancellation because of no payment of annual fees