JP2000124450A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2000124450A
JP2000124450A JP10290528A JP29052898A JP2000124450A JP 2000124450 A JP2000124450 A JP 2000124450A JP 10290528 A JP10290528 A JP 10290528A JP 29052898 A JP29052898 A JP 29052898A JP 2000124450 A JP2000124450 A JP 2000124450A
Authority
JP
Japan
Prior art keywords
region
semiconductor device
diffusion region
substrate
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10290528A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000124450A5 (enExample
Inventor
Keiichi Yamada
圭一 山田
Atsushi Maeda
敦 前田
Kenji Yoshiyama
健司 吉山
Keiichi Higashiya
恵市 東谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10290528A priority Critical patent/JP2000124450A/ja
Priority to US09/285,044 priority patent/US6064099A/en
Publication of JP2000124450A publication Critical patent/JP2000124450A/ja
Publication of JP2000124450A5 publication Critical patent/JP2000124450A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01Manufacture or treatment
    • H10D62/021Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/256Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP10290528A 1998-10-13 1998-10-13 半導体装置 Pending JP2000124450A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10290528A JP2000124450A (ja) 1998-10-13 1998-10-13 半導体装置
US09/285,044 US6064099A (en) 1998-10-13 1999-04-01 Layout of well contacts and source contacts of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10290528A JP2000124450A (ja) 1998-10-13 1998-10-13 半導体装置

Publications (2)

Publication Number Publication Date
JP2000124450A true JP2000124450A (ja) 2000-04-28
JP2000124450A5 JP2000124450A5 (enExample) 2005-12-02

Family

ID=17757204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10290528A Pending JP2000124450A (ja) 1998-10-13 1998-10-13 半導体装置

Country Status (2)

Country Link
US (1) US6064099A (enExample)
JP (1) JP2000124450A (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486264B1 (ko) * 2002-07-12 2005-05-03 삼성전자주식회사 통합 영역을 갖는 반도체 소자 및 그 제조방법
JP2007258314A (ja) * 2006-03-22 2007-10-04 Seiko Npc Corp 半導体装置の製造方法及び半導体装置
JP2010245196A (ja) * 2009-04-02 2010-10-28 Elpida Memory Inc 半導体装置およびその製造方法
JP2011108758A (ja) * 2009-11-13 2011-06-02 Fujitsu Semiconductor Ltd 高耐圧mosトランジスタおよび半導体集積回路装置、高耐圧半導体装置
JP2019004091A (ja) * 2017-06-19 2019-01-10 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2023223722A1 (ja) * 2022-05-20 2023-11-23 ソニーセミコンダクタソリューションズ株式会社 半導体装置及び電子機器
WO2025104997A1 (ja) * 2023-11-17 2025-05-22 ソニーセミコンダクタソリューションズ株式会社 半導体装置及び電子機器

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW411624B (en) * 1998-03-21 2000-11-11 Shiu Ching Shiang Structure, operation and manufacturing method of flash memory cell through channel writing and erasing
JP4091304B2 (ja) * 2002-01-07 2008-05-28 セイコーインスツル株式会社 半導体集積回路の製造方法及び半導体集積回路
TW594945B (en) * 2003-09-05 2004-06-21 Powerchip Semiconductor Corp Flash memory cell and manufacturing method thereof
US7140310B2 (en) * 2003-11-18 2006-11-28 Cnh Canada, Ltd. System and method for distributing multiple materials from an agricultural vehicle
US9553011B2 (en) * 2012-12-28 2017-01-24 Texas Instruments Incorporated Deep trench isolation with tank contact grounding

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621276A (en) * 1984-05-24 1986-11-04 Texas Instruments Incorporated Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4647956A (en) * 1985-02-12 1987-03-03 Cypress Semiconductor Corp. Back biased CMOS device with means for eliminating latchup
US4905073A (en) * 1987-06-22 1990-02-27 At&T Bell Laboratories Integrated circuit with improved tub tie
JPH0923006A (ja) * 1995-07-06 1997-01-21 Rohm Co Ltd 半導体装置
JPH1074843A (ja) * 1996-06-28 1998-03-17 Toshiba Corp 多電源集積回路および多電源集積回路システム

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486264B1 (ko) * 2002-07-12 2005-05-03 삼성전자주식회사 통합 영역을 갖는 반도체 소자 및 그 제조방법
US7112856B2 (en) 2002-07-12 2006-09-26 Samsung Electronics Co., Ltd. Semiconductor device having a merged region and method of fabrication
JP2007258314A (ja) * 2006-03-22 2007-10-04 Seiko Npc Corp 半導体装置の製造方法及び半導体装置
JP2010245196A (ja) * 2009-04-02 2010-10-28 Elpida Memory Inc 半導体装置およびその製造方法
US8378417B2 (en) 2009-04-02 2013-02-19 Elpida Memory, Inc. Semiconductor device including a well potential supply device and a vertical MOS transistor
JP2011108758A (ja) * 2009-11-13 2011-06-02 Fujitsu Semiconductor Ltd 高耐圧mosトランジスタおよび半導体集積回路装置、高耐圧半導体装置
JP2019004091A (ja) * 2017-06-19 2019-01-10 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2023223722A1 (ja) * 2022-05-20 2023-11-23 ソニーセミコンダクタソリューションズ株式会社 半導体装置及び電子機器
WO2025104997A1 (ja) * 2023-11-17 2025-05-22 ソニーセミコンダクタソリューションズ株式会社 半導体装置及び電子機器

Also Published As

Publication number Publication date
US6064099A (en) 2000-05-16

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