JP2000005421A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively prevent an unfair practice by the alternation of a circuit substrate by loading a single transmitting direction regulating means for making only the input of a signal from a game control substrate available, on a fame side control substrate controlling a frame side mechanism portion on the basis of a signal from the game control substrate. SOLUTION: The display control command data is outputted from an output port 571 of an I/O port in a game control substrate 31, and inputted to a display control CPU 101 through a buffer circuit 105 in a display control substrate 80. Further, a strobing singal is outputted from a pit of an output port 572 in synchronization with the output from an output port 57, and the signal is inputted to the display control CPU 101. An enable terminal of each buffer of the buffer circuit 105 is constantly provided with low level, and the output level of each buffer is defined by a signal level from the game control substrate 31, so that the transmission of the unfair practice signal to the game control substrate 31 side from the display control substrate 80 side can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine or a coin game machine in which a game is played in accordance with a player's operation. Related to gaming machines to be performed.

[0002]

2. Description of the Related Art As a gaming machine, a variable display device having a variable display portion whose display state can be changed is provided, and when a display result of the variable display portion becomes a predetermined specific display mode, the player is provided with a variable display device. Some are configured to shift to an advantageous specific game state. The variable display device includes a plurality of variable display units, and is generally configured to display the display results of the plurality of variable display units at different times. On the variable display section, for example, a plurality of identification information such as symbols are variably displayed. The fact that the display result of the variable display unit is a combination of predetermined specific display modes is usually referred to as “big hit”. In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0003] In addition, among the combinations of the display modes of "outside" other than the combination of "big hit", at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results are already displayed. The state in which the display mode of the variable display unit that is derived and displayed satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. A player plays a game while enjoying how to generate a big hit.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 15 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

[0005] As described above, when a big hit occurs, the state becomes extremely advantageous to the player, and there is a possibility that a fraudulent act of illegally generating a big hit may be performed. There is a possibility that the wrongdoing is performed not only from the front side of the gaming machine but also by performing unauthorized modification on various circuit boards installed on the backside of the gaming machine. If the big hits occur fraudulently, it will cause a great loss to the game store. In addition, if the loss at the game store increases, the profit that must be returned to ordinary players to make up for the loss may be reduced.

[0006]

As described above, as described above,
A game store or a general game player suffers a great loss when receiving cheating, so there is a strong demand for the emergence of gaming machines that are less susceptible to cheating. In particular, since unauthorized modification of various circuit boards installed on the back of the gaming machine is hard to be found, prevention of illegal acts due to circuit board modification in gaming machines has become an important issue.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a gaming machine that effectively prevents illegal acts due to circuit board remodeling and makes it difficult to receive illegal acts. And

[0008]

A gaming machine according to the present invention comprises:
A gaming machine in which a game board including a game area is provided in a frame, in which a game is performed in accordance with an operation of a player, wherein a game control board on which game control means for controlling game progress is mounted, and a game control board. And a frame-side control board mounted with frame-side control means for controlling the frame-side mechanical section based on a signal from the apparatus, and a signal transmission direction regulating means that enables only signal input from the game control board. It is mounted on a frame-side control board. Here, the frame-side mechanism is a mechanism installed on a portion of the game board on the frame side, and is a concept including a light-emitting component such as a non-moving lamp or LED, and a sound generating component such as a speaker. .

The signal transmission direction regulating means may be constituted by a general-purpose buffer IC circuit. In addition, buffer IC
The enable terminal of the circuit may always be set to the input / output conduction state. Further, the game control board may be provided with a signal transmission direction regulating means that enables only the output of the signal to the frame-side control board.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, an image display section 9 for variably displaying a plurality of kinds of symbols and a 7-segment L are provided.
A variable display device 8 including a variable display 10 using an ED is provided. In the image display section 9, "left", "middle",
There are three "right" symbol display areas, and these symbol display areas constitute each variable display section. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate sensor 12 that detects a hit ball that has passed through the passage gate 11. In addition, the winning ball entering the starting winning opening 14 is guided to the back of the game board 6,
It is detected by the starting port sensor 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 includes the solenoid 1
6 is opened.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. A winning ball that has entered one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count sensor 22. The winning ball from the opening / closing plate 20 is detected by the count sensor 23. At the bottom of the variable display device 8, the number of winning balls entering the starting winning opening 14 is displayed.
A start winning storage display 18 having a plurality of display units is provided. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, every time the variable display of the image display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24. Decorative lamps 25 are provided around the left and right sides of the game area 7 so as to blink during the game.
There is an out port 26 for absorbing a hit ball that does not win. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A game effect LED 28a and a game effect lamp 2
8b and 28c are provided. And in this example,
A prize ball lamp 51 that lights up when a premium ball is paid out is provided near one of the speakers 27, and a ball out lamp 52 that lights up when a supply ball runs out is provided near the other speaker 27. Further, FIG. 1 shows a pachinko gaming table 1
Also shown is a card unit 50, which is installed adjacent to and allows lending of balls by inserting a prepaid card.

A hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball passes through the passage gate 11 and is detected by the gate sensor 12, the number displayed on the variable display 10 changes to a continuously changing state. When a hit ball enters the starting winning opening 14 and is detected by the starting opening sensor 17, the symbols in the image display section 9 start rotating if the symbols can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one. The start winning memory will be described later in detail. The rotation of the image in the image display unit 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols,
It shifts to a jackpot game state. That is, the opening and closing plate 20 is
Until a certain time elapses, or a predetermined number (for example, 10
) Until the ball hits. And the opening and closing plate 2
If the hit ball wins in the specific winning area during the opening of 0 and is detected by the V count sensor 22, a continuation right is generated and the opening and closing plate 20 is opened again. The generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the image display unit 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

The mechanism board 36 includes a variable display control unit 29 for controlling the image display device 9 via the relay board 30, a game control board 31 covered with a board case 32 and mounted with a game control microcomputer, and the like. A relay board 33 for relaying a signal between the display control unit 29 and the game control board 31 is provided. In addition, a prize ball board 37 on which a payout control microcomputer or the like for controlling payout of prize balls is mounted, and a hit ball firing device 34 for firing a hit ball into the game area 7 using the rotational force of a motor are provided. . Further, on the frame side of the mechanism plate 36, a lamp control board 35 for sending signals to the game effect LEDs 28a, the game effect lamps 28b and 28c, the prize ball lamp 51, and the ball cutout lamp 52 is provided. Although not shown in FIG. 2, a sound control board for controlling the sound generation from the speaker 27 and a launch control board 91 for controlling the hit ball launching device 34 are also provided.

As shown in FIG. 3, on the back surface of the game board 6, there is provided a prize ball collecting cover 40 for guiding a prize ball that has won each prize port and a prize ball device along a predetermined prize path. I have. Out of the winning balls guided to the winning ball collecting cover 40, those winning through the opening / closing plate 20 are the ball payout device 9
7 is controlled so as to pay out a relatively large number of prize balls (for example, 15). The winnings through the starting winning opening 14 are controlled so that a ball payout device (not shown in FIG. 3) pays out a relatively small number of prize balls (for example, six). Then, the winnings through the other winning ports 24 and the winning ball device are controlled so that the ball payout device pays out a relatively medium number of prize balls (for example, 10).

In order to perform such control, signals from the winning ball detection switch 99, the starting port sensor 17, and the V count sensor 22 are sent to the game control board 31. When the ON signal of the prize ball detection switch 99 is sent to the game control board 31, a prize ball number signal is sent from the game control board 31 to the prize ball board 37. The winning is detected by the winning ball detection switch 99. In this case, the game control board 31 sends a winning ball number signal to the winning ball board 37.
For example, when the prize ball detection switch 99 is turned on in response to the start port sensor 17 being turned on, “6” is output to the prize ball number signal, and the count sensor 23 or the V count sensor 2 is output.
When the winning ball detection switch 99 is turned on in response to the turning on of “2”, “15” is output as the winning ball number signal. When these sensors do not turn on, the winning ball detection switch 9
When 9 is turned on, “10” is output as the prize ball number signal.

FIG. 4 shows a game control board (main board) 31.
FIG. 3 is a block diagram showing an example of a circuit configuration in FIG. FIG. 4 also shows the prize ball board 37, the lamp control board 35, the audio control board 70, the launch control board 91, and the display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program,
A switch circuit 5 that supplies signals from the gate sensor 12, the starting port sensor 17, the V count sensor 22, the count sensor 23, and the winning ball detection switch 99 to the basic circuit 53.
And a solenoid 16 for opening and closing the variable winning ball device 15 and a solenoid 21 for opening and closing the opening and closing plate 20.
A solenoid circuit 59 driven in accordance with a command from 3;
The start memory display 18 is turned on and off, and 7
The lamp / LED circuit 6 for driving the variable display 10 by the segment LED and blinking the decoration lamp 25
0 is included.

Further, according to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display on the image display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

A hit ball firing device 3 for hitting and firing a game ball
4 is driven by a drive motor 94 controlled by a circuit on the emission control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the operation knob 5 is controlled by the circuit on the firing control board 91.
Is controlled so that a hit ball is fired at a speed corresponding to the operation amount of the ball.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation according to the control program, and an I / O port unit 57. The ROM 54 and the RAM 55 may be built in the CPU 56 in some cases.

Further, the main board 31 is provided with an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on, and a reset pulse is given to the basic circuit 53 periodically (for example, every 2 ms) to control the game. A periodic reset circuit 66 for executing the program again from the beginning;
An address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57 is provided.

FIG. 5 is a block diagram showing a circuit configuration in the display control board 80 together with a CRT 82 for realizing the image display section 9. The display control board 80 is provided with a display control circuit 81 for controlling image display on the CRT 82. Further, a reset circuit 83 for resetting the display control circuit 81 is provided on the display control board 80.
An oscillation circuit 84 for supplying a clock signal to the display control circuit 81, a character ROM 86 for storing data representing a frequently used image, a VRAM 87 for storing image data generated by the display control circuit 81,
And a frame memory circuit 88 in which image data for one screen is set. The image data in the frame memory circuit 88 is converted into a video signal composed of an RGB color signal and a SYNC signal in synchronism with a predetermined synchronization signal.
And an image is displayed on the CRT 82. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, graphics, or symbols displayed on the CRT 82.

When the strobe signal is input from the display device circuit 63 of the main board 31, the display control circuit 81 inputs the display control command data from the display device circuit 63 and recognizes the state indicated by the command data. The display control circuit 81 generates image data to be displayed on the CRT 82 according to the state of the command data. Then, the image data is stored in the VRAM 87.

FIG. 6 is a block diagram showing an example of the configuration of the display control circuit 81. The CRT control circuit 81 includes a display control CPU 101, a VDP 103, and a control data ROM 102 in which control data is stored. The display control CPU 101 includes the display device circuit 6.
The necessary data is read from the character ROM 86 in accordance with the display control command data from the third ROM. Then, the display control CPU 101 transmits the read data to the VDP 10
Output to 3. The VDP 103 generates image data to be displayed on the CRT 82 according to the input data, and stores the image data in the VRAM 87. And VR
The image data in the AM 87 is transferred to the frame memory circuit 88. Although not shown in FIG. 6, a CRT substrate having a CRT driving circuit for driving the CRT 82 based on a video signal is provided between the display control substrate 80 and the CRT 82.

FIG. 7 is a circuit diagram showing a portion of the main board 31 and the display control board 80 related to transmission and reception of display control command data. FIG. 7 shows an output port 571 for transmitting display control command data and an output port 572 for outputting a strobe signal. In addition,
The output ports 571 and 572 are a part of the I / O port unit 57 shown in FIG.

As shown in FIG. 7, the display control command data is output from the output port 571 of the I / O port unit 57 in the basic circuit 53. In the display control board 80, display control command data is input to the display control CPU 101 via the buffer circuit 105. Further, a strobe signal is output from bit 7 of output port 572 in synchronization with the output from output port 571. In the display control board 80, the strobe signal is also supplied to the buffer circuit 105.
Is input to the display control CPU 101 via the. If the display control CPU 91 does not include an I / O port, the buffer circuit 105 and the display control CPU 101
And an I / O port is provided.

The strobe signal is supplied to the display control CPU 10.
1 is input to an IRQ2 terminal which is an interrupt input terminal. Therefore, the display control CPU 101 can know that the display control command data has been transmitted in response to the interrupt request of the IRQ2 terminal. In the interrupt control program in the display control program, display control command data input to the input port is fetched and stored.

FIG. 8 is an explanatory diagram showing display control command data transmitted from the main board 31 to the display control board 80. As shown in FIG. 8, in this embodiment, display control command data is transmitted from the main board 31 to the display control board 80 through eight signal lines of display control signals CD0 to CD7. Also, the main board 31 and the display control board 80
The signal line of the display control signal INT for transmitting the strobe signal and the power supply of the display control board 80
A supply line for supplying 5 V and +12 V and a signal line for supplying a ground level are also provided.

FIG. 9 is a timing chart showing transmission timing of display control command data given from the main board 31 to the game control board 80. Each display control data constituting the display control command data is transmitted continuously, but as shown in FIG. 9, the display control data is transmitted every 2 ms. Then, a strobe signal is output in synchronization with each display control data. The display control CPU 101 includes:
At the rising edge of the strobe signal, IRQ as shown in FIG.
Since two interrupts occur, the display control CPU 101 can fetch each display control data by the interrupt processing program.

FIG. 10 is an explanatory diagram showing an example of the display control command data. In this embodiment, it is assumed that the display control command data is composed of display control command data 1 to 8 of 8 bytes. It is assumed that the display control command data 1 to 6 are display control data used in the original game control. In addition,
FIG. 10 shows only representative display control data such as “all symbol variation display”, but other display control data indicating a reach type, display control data indicating a specific symbol, and the like are prepared. ing.

FIG. 11 is a circuit diagram showing a configuration example of the buffer circuit 105 installed on the display control board 80. In this example, a general-purpose CMOS-
74HC244 which is IC is used. 74HC
Since 244 contains eight buffers, a two-chip 74HC244 is used in this example. 74H
C244 is provided with an enable terminal, and the state of each buffer is controlled by the signal level of the enable terminal. When the signal level of the enable terminal is at a high level, the output of the buffer is in a high impedance state. When the signal level is at a low level, the output level of the buffer is the same as the input level. Here, a low level (GND level) is always given to the enable terminal.

Next, the operation of the gaming machine will be described. FIG.
2 is a flowchart showing the operation of the basic circuit 53 on the main board 31. As described above, this process is started, for example, every 2 ms by the reset pulse generated by the periodic reset circuit 66. When the basic circuit 53 is started, the basic circuit 53 first performs a stack setting process for setting a designated address of a stack pointer (step S1). Next, an initialization process is performed (step S2). In the initialization processing, the basic circuit 53
It is determined whether an error is included in the RAM 55, and if an error is included, processing such as initializing the RAM 55 is performed. Then, after performing a process of setting a command code sent to the display control board 80 in a predetermined area of the RAM 55 (step S3), a process of outputting the command code as display control data is performed (step S3).
4).

Next, a process for transmitting a predetermined command for sound generation and LED lighting control to the lamp control board 35 and the voice control board 70 is performed, and a big hit to the hall management computer via the information output circuit 64. A process for transmitting data such as information, start information, and probability variation information is performed (data output process: step S5). In addition, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S6).

Next, a process of updating each counter indicating each random number for determination used in the game control is performed (step S).
7). In step S7, the basic circuit 53 counts up (adds 1) the big hit determination random number or the like as the determination random number.

Next, the basic circuit 53 performs a special symbol process (step S8). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S9). In normal symbol processing, 7 segment LE
A corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display device 10 by D in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state. Further, the basic circuit 53 inputs the states of the gate sensor 12, the starting port sensor 17, and the count sensor 23 via the switch circuit 58, and determines whether or not each of the winning openings and the winning devices has been won (step S10). .

The basic circuit 53 further performs a process of updating the display random number (step S11). That is, the count up (addition of 1) of the random number for symbol determination and the like is performed.

The basic circuit 53 performs signal processing with the award ball substrate 37 (step S12). That is, when a predetermined condition is satisfied, a prize ball number signal is output to the prize ball substrate 37. CP for controlling the prize ball mounted on the prize ball substrate 37
U drives the ball payout device 97 according to the prize ball number signal. After that, the basic circuit 53 next executes the periodic reset circuit 6.
Step S1 until the reset pulse is given from Step S1
3 is repeated.

FIG. 13 is a flowchart showing an example of a special symbol process processing program in the basic circuit 53. The special symbol process process shown in FIG. 13 is a specific process of step S8 in the flowchart of FIG. When performing the special symbol process processing, the CPU 56 of the basic circuit 53 performs any one of steps S300 to S309 shown in FIG. 13 according to the internal state. In each process, the following processes are performed.

Special symbol change waiting process (step S30)
0): The start winning port 14 (in this embodiment, the winning port of the variable winning ball device 15) is hit and the start port sensor 17 is turned on. When the starting port sensor 17 is turned on, the starting winning memory number is increased by + if the starting winning memory number is not full.
1 and a big hit determination random number is extracted. Special symbol determination processing (step S301): When a state in which the variable display of the special symbol can be started, the number of start winning prizes is confirmed. If the number of start winning prizes is not 0, it is determined whether to make a jackpot or not according to the value of the extracted jackpot determination random number. Stop symbol setting process (step S3
02): The stop symbol of the left and right middle symbols is determined.

Reach operation setting processing (step S30)
3): Whether or not the reach operation is performed is determined according to the value of the reach determination random number, and the variation mode of the reach operation is determined according to the value of the reach random number.

All symbols change start processing (step S30)
4): The image display unit 9 is controlled so that all symbols start to change. When a background or a character is also displayed on the image display unit 9, control is performed so that display control command data corresponding to the background or character is transmitted to the display control board 80. All symbols stop waiting process (step S305): After a predetermined time has elapsed, control is performed so that all symbols displayed on the image display unit 9 are stopped. In addition, control is performed such that the left and right symbols are stopped at a predetermined timing until the timing of stopping all symbols, and display control command data corresponding to a background or a character displayed on the image display unit 9 is appropriately displayed on the display control board 80. Control to be sent to

Big hit display processing (step S306):
If the stop symbol is a combination of jackpot symbols,
The display control command data of the jackpot display is controlled to be sent to the display control board 80, and the internal state (process flag) is updated so as to shift to step S307. Otherwise, the internal state is changed to step S3.
Update to shift to 09. The combination of the big hit symbols is a combination in which the right and left middle symbols are aligned.
The circuit of the game control board 80 displays a big hit on the image display unit 9 according to the display control command data. The jackpot display is made to notify the player of the occurrence of the jackpot. Big winning opening opening process (step S307): Control for opening the big winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening.

Processing during opening of the special winning opening (step S30)
8): Control for transmitting display control command data of the special winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. If the closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S307 unless the end condition of the big hit gaming state is satisfied. If the jackpot gaming state end condition is satisfied, the internal state is updated to shift to step S309.

Big hit end processing (step S309):
A display for notifying the player that the jackpot gaming state has ended is performed. When the display is completed, the internal flags and the like are returned to the initial state, and the internal state is updated so as to shift to step S300.

A module for performing processing for transmitting display control command data in the game control program in accordance with the processing in each of the above steps (step S4 in FIG. 12).
Outputs the corresponding display control command data to the output port 57.
1 and the strobe signal to output port 5
72.

FIG. 14 is a flowchart showing an operation example of the display control data output processing (step S4). In the display control data output process, the CPU 56 first checks whether or not the data sending flag is set (step S411). If not set, it is confirmed whether or not the transmission request flag of the display control command data is set (step S412). If the transmission request flag has been set, the transmission request flag is reset (step S413). Further, the data sending flag is set and the pointer is cleared (step S414). The pointer indicates which byte in the display control command data storage area is to be transmitted.

When the data sending flag is set, the data indicated by the pointer in the display control command data storage area is transferred to the output port 57.
1 to the display control board 80 (step S4).
15). Further, the CPU 56 turns on the strobe signal.
The state is set (step S416). And 500 μs
After the wait period (step S417), the strobe signal is turned off (step S418).
Therefore, the display control data and the strobe signal are output at the timing as shown in FIG.

Next, the CPU 56 sets the value of the pointer to +
1 (step S419). Then, when the value of the pointer becomes 8, it means that transmission of all 8-byte display control command data has been completed, and the data transmission flag is reset (steps S420 and S42).
1). With the above processing, the display control command data of 8 bytes is transmitted one byte at a time in 2 ms.

FIG. 15 is a flowchart showing a display control command data receiving process of the display control CPU 101 in the display control board 80. As described above, the strobe signal from the main board 31 is transmitted to the display control CPU 10.
1 is input to the IRQ2 interrupt terminal.
The display control command data is received by the interrupt processing. Each display control data from the main board 31 is
The input is input to the input port in the display control CPU 101.

In the IRQ2 interrupt processing, the display control C
The PU 101 first checks whether or not the data receiving flag is set (step S501). If it is not set, this interrupt is caused by the transmission of the first byte of display control data, so that the pointer is cleared (step S502) and the data receiving flag is set (step S503). The pointer indicates which byte in the display control command data storage area in the RAM built in the display control CPU 101 stores the received data.

If the data receiving flag is set, the process waits until the strobe signal is turned off (step S504). The strobe signal is transmitted to the display control CPU1.
At 01, the signal is input to the IRQ2 interrupt terminal and also to the input port. Therefore, the display control CPU 101 can know that the strobe signal is OFF by checking the state of the input port. When the strobe signal is turned off, the display control CPU
101 inputs data from the input port, and stores the input data at the address indicated by the pointer in the display control command data storage area (step S505). Therefore, the display control CPU 101 receives each display control data at the timing as shown in FIG.

Then, the display control CPU 101 increments the value of the pointer by one (step S506). When the value of the pointer becomes 8, it means that the reception of the 8-byte display control command data has been completed, so that the data reception completion flag is set and the data reception flag is reset (step S507). , S508,
S509). With the above-described processing, the display control board 80 receives the 8-byte display control command data.

As shown in FIGS. 7 and 11, in the display control board 80, the low level (GND level) is always applied to the enable terminal of each buffer in the buffer circuit 105. Therefore, the output level of each buffer is determined to be the input level, that is, the signal level from the main board 31. Therefore, there is no room for a signal to be transmitted from the display control board 80 to the main board 31. Even if a circuit in the display control board 80 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side.

The basic circuit 53 of the main board 31 determines whether or not to make a big hit based on the winning start. Whether or not there is a start winning is determined in accordance with information of the starting port sensor 17 input from outside the main board 31. In the configuration of the conventional display control board, there is room for a signal from the display control board to be transmitted to the main board 31. Therefore, there is room for sending a start winning signal illegally due to unauthorized modification of the display control board 80. Eliminating as much as possible the signal lines to which signals may be externally applied to the main board 31 is effective for preventing fraud. However, as in this embodiment, the signal from the main board 31 is not displayed on the display control board 80. If a buffer that allows signals to pass through only one of them is provided in the receiving portion, the display control board 80
Therefore, a signal line to which a signal can be given to the main board 31 can be eliminated.

For example, even if the display control board 80 is modified so as to give an illegal signal for causing a big hit to the basic circuit 53 of the main board 31, the illegal signal cannot be transmitted to the main board 31. That is, unauthorized modification of the display control board 80 becomes meaningless, and such modification is prevented.

FIG. 16 is a block diagram showing another embodiment of the present invention. In this embodiment, the main substrate 3
In 1, a buffer circuit 63 is provided outside the output ports 571 and 572 as signal transmission direction regulating means. As the buffer circuit 63, for example, a general-purpose CMO
Two chips of 74HC244, which is an S-IC, are used.
The enable terminal is always given a low level (GND level). According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a possibility that a signal is given from the display control board 80 to the main board 31 can be more reliably eliminated. . Note that other circuit elements such as individual transistors may be used as the signal transmission direction regulating means.

FIG. 17 is a block diagram showing an example of a mode for inspecting display control on the main board 31. As shown in FIG. FIG.
Although not shown, a connector 110 for connecting a signal cable from the main board 31 is mounted on the display control board 80. Originally the connector 110
To the connector 21 of the inspection apparatus 200.
0, the main board 31 to the display control board 80
Are input to the inspection apparatus 200. Therefore, in the inspection apparatus 200, the signal output state from the main board 31 is checked so that the main board 31
Can be checked for display control. According to this embodiment, since there is no signal that can be transmitted from the display control board 80 to the main board 31, the display control board 80 is not inspected by the inspection apparatus, and the main board 3 is not inspected.
Checking the signal state from the main board 31
Can be completed.

FIG. 18 is a block diagram showing a signal transmitting / receiving portion of the main board 31 and a lamp control board 35 as a control board provided on the frame side. In this embodiment, the lamp control command indicating the lighting / extinguishing of the game effect LED 28a and the game effect lamps 28b and 28c provided outside the game area 7 and the interrupt signal are transmitted from the main board 31 to the lamp control board 35. Is output to Also, from the main board 31 to the lamp control board 35,
A signal indicating the lighting / extinguishing of the prize ball lamp 51 and the cutout lamp 52 is output.

As shown in FIG. 18, signals related to lamp control are output from output ports 573 and 574 of the I / O port unit 57 in the basic circuit 53. In the lamp control board 35, each signal from the main board 31 is input to the lamp control CPU 351 via the buffer circuit 355. If the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the buffer circuit 355 and the lamp control CPU 351.

FIG. 19 is an explanatory diagram showing a configuration example of the lamp control command. In this embodiment, as shown in FIG. 19, commands corresponding to each state of the game progress are defined. In the process of step S5 (see FIG. 12), the basic circuit 53 of the main board 31 outputs a predetermined command to the output port 573 and outputs an interrupt signal to the output port 574. The request is set in a special symbol processing process or the like.

On the lamp control board 35, the CPU 351 for lamp control includes a game effect LED 28a and game effect lamps 28b, 2 defined in accordance with each command.
8c according to the lighting / extinguishing pattern of 8c
8a and the game effect lamps 28b and 28c are turned on / off. The lighting / extinguishing signal is output to the game effect LED 28a and the game effect lamps 28b and 28c via an amplifier (not shown). The lighting / extinguishing pattern is stored in a built-in ROM or an external ROM of the lamp control CPU 351.

In the main board 31, the basic circuit 53
Outputs a prize ball lamp lighting instruction signal at the time of a prize ball, and outputs a ball breaking lamp lighting instruction signal when a ball breaking detection sensor installed on the game ball supply path on the back of the game board is turned on. In the lamp control board 35, those signals are input to the lamp control CPU 351 via the buffer circuit 355. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball-out lamp 52 according to those signals.

As the buffer circuit 355, for example, a 74HC244 which is a general-purpose CMOS-IC is used.
A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 side to the main board 31 side. For example, even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side.

Therefore, it is possible to eliminate a signal line from which a signal may be given from the lamp control board 35 to the main board 31. That is, the unidirectionality of a signal from the main board 31 to the lamp control board 35 is ensured, and the
Is no longer possible. As a result, for example,
Even if the lamp control board 35 is modified to give an illegal signal for causing a big hit to the basic circuit 53 of the main board 31,
Can not tell.

FIG. 20 is a block diagram showing another embodiment of the present invention. In this embodiment, the main substrate 3
In 1, a buffer circuit 62 is provided outside the output ports 573 and 574 as signal transmission direction regulating means. As the buffer circuit 62, for example, a general-purpose CMO
74HC244 which is S-IC is used. The enable terminal is always given a low level (GND level). According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the lamp control board 35 to the main board 31 is more reliably provided. Can be eliminated. Note that other circuit elements such as individual transistors may be used as the signal transmission direction regulating means.

FIG. 21 is a block diagram showing a signal transmitting / receiving portion of the main board 31 and the audio control board 70 as a frame-side control board. In this embodiment, audio reproduction data for instructing audio output of the speaker 27 provided outside the game area 7 is output from the main board 31 to the audio control board 70.

As shown in FIG. 21, the audio reproduction data is output from the output port 575 of the I / O port unit 57 in the basic circuit 53. In the audio control board 70, each signal from the main board 31 is transmitted to a buffer circuit 70.
5 to the voice control CPU 701. In addition,
When the audio control CPU 701 does not have an I / O port, the buffer circuit 705 and the audio control CPU 7
01, an I / O port is provided. Then, for example, the voice synthesizing circuit 702 based on the digital signal processor generates a voice or sound effect according to the instruction of the voice control CPU 701 and outputs it to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the voice control CPU 701 to a level corresponding to the set volume and outputs the output level to the volume amplification circuit 704. The volume amplification circuit 704 outputs the amplified audio signal to the speaker 27.

FIG. 22 is a timing chart showing an example of output of audio reproduction data. As shown in the figure, in this embodiment, a transfer request signal (S
IRQ), serial clock signal (SICK), serial data signal (SI), and transfer end signal (SRDY)
Is output. When the SIRQ goes low, the audio control CPU 701 fetches the SI one bit at a time in synchronization with SICK, and interprets the data of each SI received up to that time as one audio reproduction data when the SRDY goes low. I do. The audio reproduction data is, for example, 1
It consists of 6 bits, and one piece of audio reproduction data is output within 2 ms.

The basic circuit 53 on the main board 31 is
The data for sound reproduction is output according to each state of the game progress. The basic circuit 53 of the main board 31 performs step S5
In the process of (see FIG. 12), audio reproduction data is output according to each state of the game progress. Note that the request for outputting the audio reproduction data is set by a special symbol process process or the like.

In the voice control board 70, the voice control C
The PU 701 performs the sound synthesis circuit 70 according to the sound / sound effect pattern defined according to each sound reproduction data.
2. Output sound. The voice / sound effect pattern is stored in a built-in ROM or an external ROM of the voice control CPU 701.

As the buffer circuit 705, for example, a 74HC244 which is a general-purpose CMOS-IC is used.
A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, there is no room for a signal to be transmitted from the voice control board 70 side to the main board 31 side. For example, even if a circuit in the voice control board 70 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side.

Therefore, it is possible to eliminate a signal line to which a signal may be given from the audio control board 70 to the main board 31. Therefore, the one-way signal from the main board 31 to the audio control board 70 is ensured, and the main board 3
The possibility that the voice control board 70 influences the game control in 1 is eliminated. As a result, for example, even if the voice control board 70 is modified so as to give a fraudulent signal for causing a large hit to the basic circuit 53 of the main board 31, the fraudulent signal cannot be transmitted to the main board 31.

FIG. 23 is a block diagram showing another embodiment of the present invention. In this embodiment, the main substrate 3
1, a buffer circuit 71 is provided outside the output port 575 as signal transmission direction regulating means. As the buffer circuit 71, for example, a general-purpose CMOS-IC
74HC244 is used. The enable terminal is always given a low level (GND level).
According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked.
Signal lines from which a signal may be supplied to the main board 31 from 0 can be more reliably eliminated. In addition,
Other circuit elements such as individual transistors may be used as the signal transmission direction regulating means.

Here, on the sound control board 70, a sound volume switching circuit 703 is provided between the sound synthesizing circuit 702 and the sound volume amplifying circuit 704. The volume switching circuit 703 changes the amount of signal level attenuation according to the switch setting.
If the volume switching circuit 703 is provided in the preceding stage of 04, the current level of the control target in the volume switching circuit 703 becomes small. Therefore, current consumption is reduced and the switches used can be made inexpensive.

FIG. 24 is a block diagram showing a signal transmission / reception portion of the main board 31 and the prize ball board 37 as a frame-side control board. As shown in FIG. 24, the prize ball number signal and the prize ball enable signal are transmitted to the I / O
The signal is output from the output port 576 of the port unit 57 to the prize ball substrate 37. In the prize ball board 37, each signal from the main board 31 is transmitted to the prize ball control C
Input to PU 371. The CPU 371 for controlling the prize ball
Does not have an I / O port, an I / O port is provided between the buffer circuit 375 and the CPU 371 for controlling the prize ball.

FIG. 24 shows a prize ball detection switch 99 related to prize ball control, a ball out switch 121, a full tank switch 122 for detecting a full game ball in the surplus ball tray 4, and a prize ball for counting prize balls paid out. A count switch 123 is also shown. Winning ball detection switch 99,
The detection signals of the ball cutout switch 121, the full tank switch 122, and the prize ball count switch 123 are output to the basic circuit 53.
Is input to the CPU 56 via the input port 579 of the I / O port unit 57 in FIG. The CPU 56 is activated when the burnout switch 121 is turned on,
Turns off the prize ball possible signal when is turned on. Further, as described above, the basic circuit 53 includes the winning ball detection switch 9.
When 9 is turned on, a prize ball number signal indicating a predetermined number of prize balls is output.

On the prize ball substrate 37, a prize ball control CPU
When the prize ball number signal is input, the 371 drives the prize ball motor of the ball payout device 97 via the I / O port 372 and pays out the designated number of game balls as prize balls. When a ball lending signal is input from the card unit 50, the ball lending motor of the ball payout device 97 is driven to pay out a predetermined number of game balls.

As the buffer circuit 375, for example, 74HC244 which is a general-purpose CMOS-IC is used.
A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, the prize ball substrate 3
No signal is transmitted from the side 7 to the main board 31 side. Even if the circuit in the prize ball board 37 is tampered with,
The signal output due to the unauthorized modification is not transmitted to the main board 31 side.

Therefore, the award ball substrate 37 is moved from the main substrate 31
Can be eliminated, and there is no possibility that the prize ball board 37 will affect the game control on the main board 31. As a result,
For example, even if the prize ball substrate 37 is modified so as to give a fraudulent signal for causing a big hit to the basic circuit 53 of the main board 31, even if the fraudulent signal is changed to the main board 3
I can't tell one.

FIG. 25 is a block diagram showing another embodiment of the present invention. In this embodiment, the main substrate 3
1, a buffer circuit 61 is provided outside the output port 576 as signal transmission direction regulating means. As the buffer circuit 61, for example, a general-purpose CMOS-IC
74HC244 is used. The enable terminal is always given a low level (GND level).
According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line which may give a signal from the prize ball board 37 to the main board 31 is more reliably formed. Can be eliminated. Note that other circuit elements such as individual transistors may be used as the signal transmission direction regulating means.

FIG. 26 is a block diagram showing a signal transmitting / receiving portion of the main board 31 and the emission control board 91 as a frame-side control board. As shown in FIG. 26, the emission control signal is output from the output port 577 of the I / O port unit 57 in the basic circuit 53 to the emission control board 91.
In the launch control board 91, the launch control signal from the main board 31 is transmitted to the launch control C via the buffer circuit 915.
Input to PU911. The firing control CPU 911
Does not have an I / O port, an I / O port is provided between the buffer circuit 915 and the firing control CPU 911. In addition, FIG. 26 also shows a full tank switch 122 related to the control of launching a game ball. When the full tank switch 122 is turned on, the basic circuit 53 turns off the firing control signal.

FIG. 27 is a block diagram for explaining the operation of the firing control CPU 911. Launch control CPU
Reference numeral 911 denotes a speed control unit 151 and a sequence control unit 153.
And the torque control unit 154 is realized by software. The speed control unit 151 generates a voltage for controlling the rotation speed of the drive motor 94 in each period of a ball hitting operation for firing a game ball and a recovery / ball replenishment operation in preparation for firing the next ball. In the ball hitting operation period, a voltage that gradually increases in accordance with the rotation operation angle with respect to the operation knob 5 is generated, and in the recovery / ball replenishment operation period, a predetermined voltage is generated.

The touch sensor circuit 93 (not shown in FIG. 26) transmits a firing permission signal to the sequence control unit while the human body is in contact with the human body detection electrode (touch sensor) 93 attached to the operation knob 5. 153. Specifically, a predetermined clock signal is transmitted to the sequence control unit 153.
Output to Further, the sequence control unit 153 is supplied with a firing control signal from the main board 31. When the firing control signal and the firing permission signal are turned on, the sequence control unit 153 controls the switching of the sequence operation during the ball hitting operation period and the recovery / ball replenishment operation period, and sets the driving pattern signal and A drive voltage switching signal is generated.

As the buffer circuit 915, for example, a 74HC244 which is a general-purpose CMOS-IC is used.
A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, no signal is transmitted from the emission control board 91 side to the main board 31 side. Even if a circuit in the launch control board 91 is tampered with, a signal output by the tampering is transmitted to the main board 3.
It is not transmitted to one side.

Therefore, it is possible to eliminate a signal line from which a signal may be given from the launch control board 91 to the main board 31, and the launch control board 91 may influence the game control on the main board 31. Disappears. As a result, for example, even if the emission control board 91 is modified so as to give an illegal signal for causing a big hit to the basic circuit 53 of the main board 31, the illegal signal cannot be transmitted to the main board 31.

FIG. 28 is a block diagram showing another embodiment of the present invention. In this embodiment, the main substrate 3
1, a buffer circuit 92 is provided outside the output port 577 as signal transmission direction regulating means. As the buffer circuit 92, for example, a general-purpose CMOS-IC
74HC244 is used. The enable terminal is always given a low level (GND level).
According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked.
It is possible to more reliably eliminate a signal line from which a signal may be given to the main board 31 from 1. Note that other circuit elements such as individual transistors may be used as the signal transmission direction regulating means.

As described above, according to the present invention, the game control board for controlling the image display section 9 installed near the center of the game board, and the mechanical parts on the frame side to which the game board is assembled are provided. Lamp control board 35 for controlling, voice control board 7
0, a circuit element for ensuring the unidirectionality of the signal is provided in a portion of the prize ball board 37 and the launch control board 91 which receives a signal from the main board 31 which controls the game. Signal lines to which signals may be applied to the signal lines. As a result, it is possible to prevent an act of illegally generating a big hit.

In each of the above embodiments, the lamp control board 35 and the circuit board for controlling the frame side mechanism are used.
Voice control board 70, prize ball board 37, and launch control board 9
Although the example 1 is illustrated, when another circuit board exists according to the configuration of the gaming machine, a circuit element that ensures the unidirectionality of the signal can be provided on the circuit board.

In each of the above embodiments, the image display unit 9 using a CRT for variably displaying a plurality of types of symbols is provided.
Although the description has been given of the case of using a variable display device, a case of using a variable display device using an LCD may be used. Furthermore, the present invention can be applied to a circuit board for controlling the frame-side mechanism and a circuit board for controlling the variable display device even when a drum-type or belt-type device is used as the variable display device.

[0094]

As described above, according to the present invention, the gaming machine is constructed such that the signal transmission direction regulating means for enabling only the signal input from the game control board is provided on the frame side control board. As a result, there is an effect that it is possible to effectively prevent fraudulent acts due to the modification of the frame-side control board, thereby making it difficult to receive fraudulent acts on the gaming machine.

The signal transmission direction regulating means is a general-purpose buffer I.
In the case where the circuit is constituted by the C circuit, it is possible to easily prevent the fraudulent act due to the modification of the frame-side control board without employing a special circuit structure. When the enable terminal of the buffer IC circuit is always set to the input / output conduction state, the output level of the buffer IC circuit is determined to be the signal level from the game control board. There is no room for the signal to be transmitted to the game control board side, and the irreversibility of the signal can be reliably achieved.

In the case where the game control board is also provided with a signal transmission direction regulating means for enabling only the signal output to the frame-side control board, a signal is sent from the frame-side control board to the game control board. Inputting is more reliably prevented.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing an example of a circuit configuration in the game control board.

FIG. 5 is a block diagram showing a circuit configuration in a display control board.

FIG. 6 is a block diagram illustrating an example of a configuration of a display control circuit.

FIG. 7 is a circuit diagram showing a portion related to transmission and reception of display control command data on the main board and the display control board.

FIG. 8 is an explanatory diagram showing display control command data.

FIG. 9 is a timing chart showing transmission timing of display control command data.

FIG. 10 is an explanatory diagram illustrating an example of display control command data.

FIG. 11 is a circuit diagram illustrating a configuration example of a buffer circuit installed on a display control board.

FIG. 12 is a flowchart showing main processing of the basic circuit.

FIG. 13 is a flowchart showing a special symbol process process.

FIG. 14 is a flowchart illustrating an operation example of display control data output processing.

FIG. 15 is a flowchart showing a display control command data receiving process of the display control CPU.

FIG. 16 is a block diagram showing another embodiment of a portion related to transmission and reception of display control command data in the main board and the display control board.

FIG. 17 is a block diagram showing an example of a mode for inspecting display control on a main board.

FIG. 18 is a block diagram illustrating a signal transmission / reception portion of the main board and the lamp control board.

FIG. 19 is an explanatory diagram showing a configuration example of a lamp control command.

FIG. 20 is a block diagram showing another embodiment of a signal transmitting / receiving portion in the main board and the lamp control board.

FIG. 21 is a block diagram illustrating a signal transmission / reception portion of the main board and the audio control board.

FIG. 22 is a timing chart showing an output example of audio reproduction data.

FIG. 23 is a block diagram showing another embodiment of the signal transmission / reception portion in the main board and the voice control board.

FIG. 24 is a block diagram showing a signal transmission / reception portion of the main board and the prize ball board.

FIG. 25 is a block diagram showing another embodiment of the signal transmission / reception portion on the main board and the prize ball board.

FIG. 26 is a block diagram illustrating a signal transmission / reception portion of the main board and the emission control board.

FIG. 27 is a block diagram for explaining the operation of the firing control CPU.

FIG. 28 is a block diagram showing another embodiment of a signal transmission / reception portion in the main board and the emission control board.

[Explanation of symbols]

 14 Starting Winning Port 15 Variable Winning Ball Device 17 Starting Port Sensor 31 Game Control Board (Main Board) 35 Lamp Control Board 37 Winning Ball Board 53 Basic Circuit 61, 62, 63, 71, 92 Buffer Circuit 70 Voice Control Board 80 Display Control Substrate 105 Buffer circuit 355, 375, 705, 915 Buffer circuit

Claims (4)

[Claims] 1. A game machine in which a game board including a game area is provided in a frame and a game is performed according to an operation of a player, and a game control board on which game control means for controlling game progress is mounted. And a frame-side control board mounted with frame-side control means for controlling a frame-side mechanism based on a signal from the game control board, wherein the frame-side control board includes: A gaming machine comprising a signal transmission direction regulating means for enabling only signal input. 2. The gaming machine according to claim 1, wherein the signal transmission direction regulating means is constituted by a general-purpose buffer IC circuit. 3. An enable terminal of a buffer IC circuit,
3. The gaming machine according to claim 2, wherein the gaming machine is always set to the input / output conduction state. 4. The gaming machine according to claim 1, wherein the game control board is provided with a signal transmission direction regulating means for enabling only output of a signal to the frame-side control board.