ITMI922003A1 - Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channeling - Google Patents
Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channelingInfo
- Publication number
- ITMI922003A1 ITMI922003A1 IT002003A ITMI922003A ITMI922003A1 IT MI922003 A1 ITMI922003 A1 IT MI922003A1 IT 002003 A IT002003 A IT 002003A IT MI922003 A ITMI922003 A IT MI922003A IT MI922003 A1 ITMI922003 A1 IT MI922003A1
- Authority
- IT
- Italy
- Prior art keywords
- semi
- low
- regions implanted
- conductors
- channeling
- Prior art date
Links
- 230000005465 channeling Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITMI922003A IT1256362B (it) | 1992-08-19 | 1992-08-19 | Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channeling |
JP5180263A JPH07106275A (ja) | 1992-08-19 | 1993-07-21 | 半導体上にチャネリング現象を起こす危険性の低い注入領域を形成する方法 |
EP93111968A EP0588032B1 (en) | 1992-08-19 | 1993-07-27 | Process for forming implanted regions with lowered channeling risk on semiconductors |
DE69330986T DE69330986T2 (de) | 1992-08-19 | 1993-07-27 | Verfahren zur Bildung implantierter Gebiete mit einem reduzierten Channeling-Risiko in Halbleitern |
US08/106,037 US5436177A (en) | 1992-08-19 | 1993-08-12 | Process for forming implanted regions with lowered channeling risk on semiconductors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITMI922003A IT1256362B (it) | 1992-08-19 | 1992-08-19 | Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channeling |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI922003A0 ITMI922003A0 (it) | 1992-08-19 |
ITMI922003A1 true ITMI922003A1 (it) | 1994-02-19 |
IT1256362B IT1256362B (it) | 1995-12-04 |
Family
ID=11363880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI922003A IT1256362B (it) | 1992-08-19 | 1992-08-19 | Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channeling |
Country Status (5)
Country | Link |
---|---|
US (1) | US5436177A (it) |
EP (1) | EP0588032B1 (it) |
JP (1) | JPH07106275A (it) |
DE (1) | DE69330986T2 (it) |
IT (1) | IT1256362B (it) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0622832B1 (en) * | 1993-03-17 | 2000-05-31 | Canon Kabushiki Kaisha | Method of connecting a wiring with a semiconductor region and semiconductor device obtained by this method |
US5883566A (en) * | 1997-02-24 | 1999-03-16 | International Business Machines Corporation | Noise-isolated buried resistor |
US6090656A (en) | 1998-05-08 | 2000-07-18 | Lsi Logic | Linear capacitor and process for making same |
US7217613B2 (en) * | 2001-04-11 | 2007-05-15 | Newport Fab, Llc | Low cost fabrication of high resistivity resistors |
US7122436B2 (en) * | 2004-09-16 | 2006-10-17 | Lsi Logic Corporation | Techniques for forming passive devices during semiconductor back-end processing |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4208781A (en) * | 1976-09-27 | 1980-06-24 | Texas Instruments Incorporated | Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer |
US4290185A (en) * | 1978-11-03 | 1981-09-22 | Mostek Corporation | Method of making an extremely low current load device for integrated circuit |
JPS55107244A (en) * | 1979-02-09 | 1980-08-16 | Toshiba Corp | Manufacture of semiconductor device |
US4367580A (en) * | 1980-03-21 | 1983-01-11 | Texas Instruments Incorporated | Process for making polysilicon resistors |
US4391650A (en) * | 1980-12-22 | 1983-07-05 | Ncr Corporation | Method for fabricating improved complementary metal oxide semiconductor devices |
FR2534415A1 (fr) * | 1982-10-07 | 1984-04-13 | Cii Honeywell Bull | Procede de fabrication de resistances electriques dans un materiau semi-conducteur polycristallin et dispositif a circuits integres resultant |
US4489104A (en) * | 1983-06-03 | 1984-12-18 | Industrial Technology Research Institute | Polycrystalline silicon resistor having limited lateral diffusion |
JPS6063961A (ja) * | 1983-08-30 | 1985-04-12 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS61191070A (ja) * | 1985-02-20 | 1986-08-25 | Toshiba Corp | 半導体装置の製造方法 |
US4637836A (en) * | 1985-09-23 | 1987-01-20 | Rca Corporation | Profile control of boron implant |
US4866002A (en) * | 1985-11-26 | 1989-09-12 | Fuji Photo Film Co., Ltd. | Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof |
JPS62169472A (ja) * | 1986-01-22 | 1987-07-25 | Hitachi Ltd | 半導体集積回路装置 |
US5304502A (en) * | 1988-11-08 | 1994-04-19 | Yamaha Corporation | Process of fabricating semiconductor integrated circuit having conductive strips used as resistor and gate electrode of component transistor |
JPH0434966A (ja) * | 1990-05-30 | 1992-02-05 | Seiko Instr Inc | 半導体装置の製造方法 |
US5141597A (en) * | 1990-11-14 | 1992-08-25 | United Technologies Corporation | Thin polysilicon resistors |
US5204279A (en) * | 1991-06-03 | 1993-04-20 | Sgs-Thomson Microelectronics, Inc. | Method of making SRAM cell and structure with polycrystalline p-channel load devices |
EP0524025A3 (en) * | 1991-07-18 | 1993-03-10 | Sgs-Thomson Microelectronics, Inc. | High-value resistors and methods for making same |
US5236857A (en) * | 1991-10-30 | 1993-08-17 | Texas Instruments Incorporated | Resistor structure and process |
-
1992
- 1992-08-19 IT ITMI922003A patent/IT1256362B/it active IP Right Grant
-
1993
- 1993-07-21 JP JP5180263A patent/JPH07106275A/ja active Pending
- 1993-07-27 EP EP93111968A patent/EP0588032B1/en not_active Expired - Lifetime
- 1993-07-27 DE DE69330986T patent/DE69330986T2/de not_active Expired - Fee Related
- 1993-08-12 US US08/106,037 patent/US5436177A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0588032A2 (en) | 1994-03-23 |
IT1256362B (it) | 1995-12-04 |
JPH07106275A (ja) | 1995-04-21 |
ITMI922003A0 (it) | 1992-08-19 |
DE69330986D1 (de) | 2001-11-29 |
US5436177A (en) | 1995-07-25 |
EP0588032B1 (en) | 2001-10-24 |
DE69330986T2 (de) | 2002-06-13 |
EP0588032A3 (en) | 1996-01-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19960828 |