IT8921619A0 - Procedimento per la realizzazione di celle di memoria eeprom a singolo livello di polisilicio e ossido sottile utilizzando ossidazione differenziale. - Google Patents

Procedimento per la realizzazione di celle di memoria eeprom a singolo livello di polisilicio e ossido sottile utilizzando ossidazione differenziale.

Info

Publication number
IT8921619A0
IT8921619A0 IT8921619A IT2161989A IT8921619A0 IT 8921619 A0 IT8921619 A0 IT 8921619A0 IT 8921619 A IT8921619 A IT 8921619A IT 2161989 A IT2161989 A IT 2161989A IT 8921619 A0 IT8921619 A0 IT 8921619A0
Authority
IT
Italy
Prior art keywords
polysilic
creation
procedure
memory cells
eeprom memory
Prior art date
Application number
IT8921619A
Other languages
English (en)
Other versions
IT1232354B (it
Inventor
Paolo Ghezzi
Carlo Riva
Grazia Valentini
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8921619A priority Critical patent/IT1232354B/it
Publication of IT8921619A0 publication Critical patent/IT8921619A0/it
Priority to EP90202302A priority patent/EP0416687B1/en
Priority to DE69030544T priority patent/DE69030544T2/de
Priority to JP2226838A priority patent/JP2568940B2/ja
Priority to US07/574,677 priority patent/US5132239A/en
Application granted granted Critical
Publication of IT1232354B publication Critical patent/IT1232354B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
IT8921619A 1989-09-04 1989-09-04 Procedimento per la realizzazione di celle di memoria eeprom a singolo livello di polisilicio e ossido sottile utilizzando ossidazione differenziale. IT1232354B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8921619A IT1232354B (it) 1989-09-04 1989-09-04 Procedimento per la realizzazione di celle di memoria eeprom a singolo livello di polisilicio e ossido sottile utilizzando ossidazione differenziale.
EP90202302A EP0416687B1 (en) 1989-09-04 1990-08-28 Process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide by using differential oxidation
DE69030544T DE69030544T2 (de) 1989-09-04 1990-08-28 Verfahren zur Herstellung von EEPROM-Speicherzellen mit einer einzigen Polysiliziumebene und dünnem Oxyd mittels differenzierter Oxydation
JP2226838A JP2568940B2 (ja) 1989-09-04 1990-08-30 一層ポリシリコンおよび差別化酸化を用いた薄い酸化膜を有するｅｅｐｒｏｍメモリセルの製造方法
US07/574,677 US5132239A (en) 1989-09-04 1990-08-30 Process for manufacturing eeprom memory cells having a single level of polysilicon and thin oxide by using differential oxidation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8921619A IT1232354B (it) 1989-09-04 1989-09-04 Procedimento per la realizzazione di celle di memoria eeprom a singolo livello di polisilicio e ossido sottile utilizzando ossidazione differenziale.

Publications (2)

Publication Number Publication Date
IT8921619A0 true IT8921619A0 (it) 1989-09-04
IT1232354B IT1232354B (it) 1992-01-28

Family

ID=11184419

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8921619A IT1232354B (it) 1989-09-04 1989-09-04 Procedimento per la realizzazione di celle di memoria eeprom a singolo livello di polisilicio e ossido sottile utilizzando ossidazione differenziale.

Country Status (5)

Country Link
US (1) US5132239A (it)
EP (1) EP0416687B1 (it)
JP (1) JP2568940B2 (it)
DE (1) DE69030544T2 (it)
IT (1) IT1232354B (it)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225700A (en) * 1991-06-28 1993-07-06 Texas Instruments Incorporated Circuit and method for forming a non-volatile memory cell
EP0610643B1 (en) * 1993-02-11 1997-09-10 STMicroelectronics S.r.l. EEPROM cell and peripheral MOS transistor
US5440159A (en) * 1993-09-20 1995-08-08 Atmel Corporation Single layer polysilicon EEPROM having uniform thickness gate oxide/capacitor dielectric layer
JP2924622B2 (ja) * 1993-12-28 1999-07-26 日本電気株式会社 半導体装置の製造方法
DE69429815T2 (de) * 1994-11-24 2002-09-26 Stmicroelectronics S.R.L., Agrate Brianza Integrierte EEPROM-Schaltung mit reduziertem Substrat-Effekt und Zwei-Wannen-Herstellungsverfahren hiervon
US6534364B1 (en) * 1994-12-05 2003-03-18 Texas Instruments Incorporated Tunnel diode layout for an EEPROM cell for protecting the tunnel diode region
US7067442B1 (en) * 1995-12-26 2006-06-27 Micron Technology, Inc. Method to avoid threshold voltage shift in thicker dielectric films
US6462394B1 (en) 1995-12-26 2002-10-08 Micron Technology, Inc. Device configured to avoid threshold voltage shift in a dielectric film
EP0820103B1 (en) * 1996-07-18 2002-10-02 STMicroelectronics S.r.l. Single polysilicon level flash EEPROM cell and manufacturing process therefor
US5904524A (en) * 1996-08-08 1999-05-18 Altera Corporation Method of making scalable tunnel oxide window with no isolation edges
JPH11144486A (ja) * 1997-10-31 1999-05-28 Oko Denshi Kofun Yugenkoshi 高密度メモリ用メモリ冗長回路
FR2776829B1 (fr) 1998-03-31 2000-06-16 Sgs Thomson Microelectronics Procede de fabrication d'un point memoire en technologie bicmos
US6177703B1 (en) 1999-05-28 2001-01-23 Vlsi Technology, Inc. Method and apparatus for producing a single polysilicon flash EEPROM having a select transistor and a floating gate transistor
US6272050B1 (en) 1999-05-28 2001-08-07 Vlsi Technology, Inc. Method and apparatus for providing an embedded flash-EEPROM technology
US6596587B1 (en) * 2002-06-03 2003-07-22 Lattice Semiconductor Corporation Shallow junction EEPROM device and process for fabricating the device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7500550A (nl) * 1975-01-17 1976-07-20 Philips Nv Halfgeleider-geheugeninrichting.
US4049477A (en) * 1976-03-02 1977-09-20 Hewlett-Packard Company Method for fabricating a self-aligned metal oxide field effect transistor
DE3174638D1 (en) * 1980-10-29 1986-06-19 Fairchild Camera Instr Co A method of fabricating a self-aligned integrated circuit structure using differential oxide growth
JPS5776877A (en) * 1980-10-30 1982-05-14 Fujitsu Ltd Semiconductor memory device and manufacture thereof
JPS6362382A (ja) * 1986-09-03 1988-03-18 Nec Corp 浮遊ゲ−ト型不揮発性半導体記憶装置およびその製造方法
IT1198109B (it) * 1986-11-18 1988-12-21 Sgs Microelettronica Spa Cella di memoria eeprom a singolo livello di polisilicio con zona di ossido di tunnel
JPH01152650A (ja) * 1987-12-09 1989-06-15 Sharp Corp 半導体集積回路装置の製造方法
JPH02218167A (ja) * 1989-02-18 1990-08-30 Matsushita Electron Corp 半導体記憶装置の製造方法

Also Published As

Publication number Publication date
IT1232354B (it) 1992-01-28
DE69030544T2 (de) 1997-08-21
US5132239A (en) 1992-07-21
JP2568940B2 (ja) 1997-01-08
JPH03116972A (ja) 1991-05-17
DE69030544D1 (de) 1997-05-28
EP0416687B1 (en) 1997-04-23
EP0416687A2 (en) 1991-03-13
EP0416687A3 (en) 1991-10-02

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970929