JPS5776877A - Semiconductor memory device and manufacture thereof - Google Patents
Semiconductor memory device and manufacture thereofInfo
- Publication number
- JPS5776877A JPS5776877A JP15250980A JP15250980A JPS5776877A JP S5776877 A JPS5776877 A JP S5776877A JP 15250980 A JP15250980 A JP 15250980A JP 15250980 A JP15250980 A JP 15250980A JP S5776877 A JPS5776877 A JP S5776877A
- Authority
- JP
- Japan
- Prior art keywords
- drain region
- oxide film
- tunnel oxide
- eeprom
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000012535 impurity Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To improve the reliability of EEPROM (PROM in which electrical eliminating is possible) is which electrical eliminating and writing is possible by a method wherein a drain region under a tunnel oxide film is kept away by forming the drain region roughly into an L-shape and a stable tunnel oxide film is formed. CONSTITUTION:In EEPROM which is composed of a floating gate electrode 14 formed on a surface of a p type semiconductor substrate 11 with a gate insulating film 13 underneath, a control gate electrode 15, a source region 16 and a drain region 17, the roughly L-shaped drain region 17 to which a drain electrode is connected is kept away from the drain region 17' under a tunnel oxide film 20 which is formed by using properly two kinds of impurities As and P. Here two memory elements are formed symmetically and the drain regions 17, 17' form a T-shape. With above method the stable tunnel oxide film 20 is obtained and the reliability of EEPROM is improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15250980A JPS5776877A (en) | 1980-10-30 | 1980-10-30 | Semiconductor memory device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15250980A JPS5776877A (en) | 1980-10-30 | 1980-10-30 | Semiconductor memory device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5776877A true JPS5776877A (en) | 1982-05-14 |
Family
ID=15542001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15250980A Pending JPS5776877A (en) | 1980-10-30 | 1980-10-30 | Semiconductor memory device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5776877A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61166079A (en) * | 1984-09-25 | 1986-07-26 | エツセジ−エツセ−アテイイ−エツセ・コンポネンテイ・エレツトロニ−チ・ソチエタ・ペル・アノニマ | Durable memory cell and manufacture thereof |
JPS61186945A (en) * | 1985-02-15 | 1986-08-20 | Fuji Photo Film Co Ltd | Photographing device |
US4861730A (en) * | 1988-01-25 | 1989-08-29 | Catalyst Semiconductor, Inc. | Process for making a high density split gate nonvolatile memory cell |
US5132239A (en) * | 1989-09-04 | 1992-07-21 | Sgs-Thomson Microelectronics S.R.L. | Process for manufacturing eeprom memory cells having a single level of polysilicon and thin oxide by using differential oxidation |
US5215934A (en) * | 1989-12-21 | 1993-06-01 | Tzeng Jyh Cherng J | Process for reducing program disturbance in eeprom arrays |
US5284786A (en) * | 1992-08-14 | 1994-02-08 | National Semiconductor Corporation | Method of making a split floating gate EEPROM cell |
-
1980
- 1980-10-30 JP JP15250980A patent/JPS5776877A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61166079A (en) * | 1984-09-25 | 1986-07-26 | エツセジ−エツセ−アテイイ−エツセ・コンポネンテイ・エレツトロニ−チ・ソチエタ・ペル・アノニマ | Durable memory cell and manufacture thereof |
JPH0587031B2 (en) * | 1984-09-25 | 1993-12-15 | Ates Componenti Elettron | |
JPS61186945A (en) * | 1985-02-15 | 1986-08-20 | Fuji Photo Film Co Ltd | Photographing device |
US4861730A (en) * | 1988-01-25 | 1989-08-29 | Catalyst Semiconductor, Inc. | Process for making a high density split gate nonvolatile memory cell |
US5132239A (en) * | 1989-09-04 | 1992-07-21 | Sgs-Thomson Microelectronics S.R.L. | Process for manufacturing eeprom memory cells having a single level of polysilicon and thin oxide by using differential oxidation |
US5215934A (en) * | 1989-12-21 | 1993-06-01 | Tzeng Jyh Cherng J | Process for reducing program disturbance in eeprom arrays |
US5284786A (en) * | 1992-08-14 | 1994-02-08 | National Semiconductor Corporation | Method of making a split floating gate EEPROM cell |
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