IT8819946A0 - Sistema di elaborazione comprendente un dispositivo di arbitrato di accesso diretto in memoria (dma) per una pluralita' di unita' periferiche collegate al sistema. - Google Patents

Sistema di elaborazione comprendente un dispositivo di arbitrato di accesso diretto in memoria (dma) per una pluralita' di unita' periferiche collegate al sistema.

Info

Publication number
IT8819946A0
IT8819946A0 IT8819946A IT1994688A IT8819946A0 IT 8819946 A0 IT8819946 A0 IT 8819946A0 IT 8819946 A IT8819946 A IT 8819946A IT 1994688 A IT1994688 A IT 1994688A IT 8819946 A0 IT8819946 A0 IT 8819946A0
Authority
IT
Italy
Prior art keywords
dma
memory access
direct memory
units connected
peripheral units
Prior art date
Application number
IT8819946A
Other languages
English (en)
Other versions
IT1217359B (it
Inventor
Ian A Concilio
Jeffrey A Hawthorne
Chester Asbury Heath
Jorge Eduardo Lenta
Long D Nguyen
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8819946A0 publication Critical patent/IT8819946A0/it
Application granted granted Critical
Publication of IT1217359B publication Critical patent/IT1217359B/it

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
IT19946/88A 1987-03-27 1988-03-25 Sistema di elaborazione comprendente un dispositivo di arbitrato di accesso diretto in memoria (dma) per una pluralita' di unita' periferiche collegate al sistema IT1217359B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3078887A 1987-03-27 1987-03-27

Publications (2)

Publication Number Publication Date
IT8819946A0 true IT8819946A0 (it) 1988-03-25
IT1217359B IT1217359B (it) 1990-03-22

Family

ID=21856040

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19946/88A IT1217359B (it) 1987-03-27 1988-03-25 Sistema di elaborazione comprendente un dispositivo di arbitrato di accesso diretto in memoria (dma) per una pluralita' di unita' periferiche collegate al sistema

Country Status (19)

Country Link
EP (1) EP0283580B1 (it)
JP (1) JPH0724044B2 (it)
KR (1) KR950008228B1 (it)
CN (1) CN1012295B (it)
AR (1) AR244899A1 (it)
AT (1) ATE75865T1 (it)
BE (1) BE1001290A4 (it)
BR (1) BR8800739A (it)
CA (1) CA1299295C (it)
DE (1) DE3778877D1 (it)
ES (1) ES2032288T3 (it)
FR (1) FR2613096A1 (it)
GB (1) GB2202975B (it)
GR (1) GR3004930T3 (it)
HK (1) HK65392A (it)
IT (1) IT1217359B (it)
MY (1) MY103351A (it)
NL (1) NL185312C (it)
SG (1) SG67992G (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7089344B1 (en) * 2000-06-09 2006-08-08 Motorola, Inc. Integrated processor platform supporting wireless handheld multi-media devices
JP2010165175A (ja) 2009-01-15 2010-07-29 Internatl Business Mach Corp <Ibm> バスの使用権を制御する装置および方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603935A (en) * 1969-05-12 1971-09-07 Xerox Corp Memory port priority access system with inhibition of low priority lock-out
IT971304B (it) * 1972-11-29 1974-04-30 Honeywell Inf Systems Sistema di accesso a priorita variabile dinamicamente
US4281381A (en) * 1979-05-14 1981-07-28 Bell Telephone Laboratories, Incorporated Distributed first-come first-served bus allocation apparatus
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units

Also Published As

Publication number Publication date
SG67992G (en) 1992-09-04
EP0283580B1 (en) 1992-05-06
NL8800737A (nl) 1988-10-17
NL185312C (nl) 1990-03-01
IT1217359B (it) 1990-03-22
ES2032288T3 (es) 1993-02-01
BE1001290A4 (fr) 1989-09-19
CN1012295B (zh) 1991-04-03
EP0283580A1 (en) 1988-09-28
JPS63244161A (ja) 1988-10-11
CA1299295C (en) 1992-04-21
FR2613096A1 (fr) 1988-09-30
BR8800739A (pt) 1988-10-04
GB2202975A (en) 1988-10-05
ATE75865T1 (de) 1992-05-15
JPH0724044B2 (ja) 1995-03-15
NL185312B (nl) 1989-10-02
DE3778877D1 (de) 1992-06-11
AR244899A1 (es) 1993-11-30
HK65392A (en) 1992-09-11
KR950008228B1 (ko) 1995-07-26
MY103351A (en) 1993-06-30
CN88100963A (zh) 1988-12-28
GB8728921D0 (en) 1988-01-27
KR880011679A (ko) 1988-10-29
GR3004930T3 (it) 1993-04-28
GB2202975B (en) 1991-09-25

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