ATE75865T1 - Rechnersystem mit kanaldirektspeicherzugriffsarbitrierung. - Google Patents

Rechnersystem mit kanaldirektspeicherzugriffsarbitrierung.

Info

Publication number
ATE75865T1
ATE75865T1 AT87118542T AT87118542T ATE75865T1 AT E75865 T1 ATE75865 T1 AT E75865T1 AT 87118542 T AT87118542 T AT 87118542T AT 87118542 T AT87118542 T AT 87118542T AT E75865 T1 ATE75865 T1 AT E75865T1
Authority
AT
Austria
Prior art keywords
direct
computer system
memory access
channel memory
access arbitration
Prior art date
Application number
AT87118542T
Other languages
English (en)
Inventor
Ian Anthony Concilio
Jeffrey Alan Hawthorne
Chester Asbury Heath
Jorge Eduardo Lenta
Long Duy Nguyen
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE75865T1 publication Critical patent/ATE75865T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
AT87118542T 1987-03-27 1987-12-15 Rechnersystem mit kanaldirektspeicherzugriffsarbitrierung. ATE75865T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3078887A 1987-03-27 1987-03-27
EP87118542A EP0283580B1 (de) 1987-03-27 1987-12-15 Rechnersystem mit Kanaldirektspeicherzugriffsarbitrierung

Publications (1)

Publication Number Publication Date
ATE75865T1 true ATE75865T1 (de) 1992-05-15

Family

ID=21856040

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87118542T ATE75865T1 (de) 1987-03-27 1987-12-15 Rechnersystem mit kanaldirektspeicherzugriffsarbitrierung.

Country Status (19)

Country Link
EP (1) EP0283580B1 (de)
JP (1) JPH0724044B2 (de)
KR (1) KR950008228B1 (de)
CN (1) CN1012295B (de)
AR (1) AR244899A1 (de)
AT (1) ATE75865T1 (de)
BE (1) BE1001290A4 (de)
BR (1) BR8800739A (de)
CA (1) CA1299295C (de)
DE (1) DE3778877D1 (de)
ES (1) ES2032288T3 (de)
FR (1) FR2613096A1 (de)
GB (1) GB2202975B (de)
GR (1) GR3004930T3 (de)
HK (1) HK65392A (de)
IT (1) IT1217359B (de)
MY (1) MY103351A (de)
NL (1) NL185312C (de)
SG (1) SG67992G (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7089344B1 (en) * 2000-06-09 2006-08-08 Motorola, Inc. Integrated processor platform supporting wireless handheld multi-media devices
JP2010165175A (ja) 2009-01-15 2010-07-29 Internatl Business Mach Corp <Ibm> バスの使用権を制御する装置および方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603935A (en) * 1969-05-12 1971-09-07 Xerox Corp Memory port priority access system with inhibition of low priority lock-out
IT971304B (it) * 1972-11-29 1974-04-30 Honeywell Inf Systems Sistema di accesso a priorita variabile dinamicamente
US4281381A (en) * 1979-05-14 1981-07-28 Bell Telephone Laboratories, Incorporated Distributed first-come first-served bus allocation apparatus
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units

Also Published As

Publication number Publication date
FR2613096A1 (fr) 1988-09-30
EP0283580B1 (de) 1992-05-06
AR244899A1 (es) 1993-11-30
BR8800739A (pt) 1988-10-04
NL185312B (nl) 1989-10-02
BE1001290A4 (fr) 1989-09-19
MY103351A (en) 1993-06-30
JPH0724044B2 (ja) 1995-03-15
DE3778877D1 (de) 1992-06-11
CA1299295C (en) 1992-04-21
CN88100963A (zh) 1988-12-28
HK65392A (en) 1992-09-11
IT1217359B (it) 1990-03-22
KR880011679A (ko) 1988-10-29
GB2202975B (en) 1991-09-25
GB2202975A (en) 1988-10-05
NL185312C (nl) 1990-03-01
CN1012295B (zh) 1991-04-03
KR950008228B1 (ko) 1995-07-26
GB8728921D0 (en) 1988-01-27
ES2032288T3 (es) 1993-02-01
IT8819946A0 (it) 1988-03-25
SG67992G (en) 1992-09-04
NL8800737A (nl) 1988-10-17
EP0283580A1 (de) 1988-09-28
GR3004930T3 (de) 1993-04-28
JPS63244161A (ja) 1988-10-11

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties