IT8706621A0 - Procedimento di fabbricazione di un dispositivo integrato monolitico a semiconduttore avente strati epitassiali a bassa concentrazione di impurita' - Google Patents

Procedimento di fabbricazione di un dispositivo integrato monolitico a semiconduttore avente strati epitassiali a bassa concentrazione di impurita'

Info

Publication number
IT8706621A0
IT8706621A0 IT8706621A IT662187A IT8706621A0 IT 8706621 A0 IT8706621 A0 IT 8706621A0 IT 8706621 A IT8706621 A IT 8706621A IT 662187 A IT662187 A IT 662187A IT 8706621 A0 IT8706621 A0 IT 8706621A0
Authority
IT
Italy
Prior art keywords
impurities
semiconductor integrated
low concentration
integrated device
manufacturing procedure
Prior art date
Application number
IT8706621A
Other languages
English (en)
Other versions
IT1221587B (it
Inventor
Salvatore Musumeci
Raffaele Zambrano
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT06621/87A priority Critical patent/IT1221587B/it
Publication of IT8706621A0 publication Critical patent/IT8706621A0/it
Priority to EP88201845A priority patent/EP0307032B1/en
Priority to DE3852362T priority patent/DE3852362T2/de
Priority to JP63222602A priority patent/JPH0195552A/ja
Priority to US07/241,269 priority patent/US4889822A/en
Application granted granted Critical
Publication of IT1221587B publication Critical patent/IT1221587B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT06621/87A 1987-09-07 1987-09-07 Procedimento di fabbricazione di un dispositivo integrato monolitico a semiconduttore avente strati epitas siali a bassa concentrazione di impurita' IT1221587B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT06621/87A IT1221587B (it) 1987-09-07 1987-09-07 Procedimento di fabbricazione di un dispositivo integrato monolitico a semiconduttore avente strati epitas siali a bassa concentrazione di impurita'
EP88201845A EP0307032B1 (en) 1987-09-07 1988-08-30 Manufacturing process for a monolithic semiconductor device having multiple epitaxial layers with a low concentration of impurities
DE3852362T DE3852362T2 (de) 1987-09-07 1988-08-30 Verfahren zur Herstellung eines monolithischen Halbleiterbauelementes mit epitaxischer Mehrschichtstruktur und geringer Konzentration an Verunreinigungen.
JP63222602A JPH0195552A (ja) 1987-09-07 1988-09-07 モノリシック集積半導体装置の製造方法
US07/241,269 US4889822A (en) 1987-09-07 1988-09-07 Manufacturing process for a monolithic integrated semiconductor device having multiple epitaxial layers with a low concentration of impurities

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT06621/87A IT1221587B (it) 1987-09-07 1987-09-07 Procedimento di fabbricazione di un dispositivo integrato monolitico a semiconduttore avente strati epitas siali a bassa concentrazione di impurita'

Publications (2)

Publication Number Publication Date
IT8706621A0 true IT8706621A0 (it) 1987-09-07
IT1221587B IT1221587B (it) 1990-07-12

Family

ID=11121534

Family Applications (1)

Application Number Title Priority Date Filing Date
IT06621/87A IT1221587B (it) 1987-09-07 1987-09-07 Procedimento di fabbricazione di un dispositivo integrato monolitico a semiconduttore avente strati epitas siali a bassa concentrazione di impurita'

Country Status (5)

Country Link
US (1) US4889822A (it)
EP (1) EP0307032B1 (it)
JP (1) JPH0195552A (it)
DE (1) DE3852362T2 (it)
IT (1) IT1221587B (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5246871A (en) * 1989-06-16 1993-09-21 Sgs-Thomson Microelectronics S.R.L. Method of manufacturing a semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip
IT1234252B (it) * 1989-06-16 1992-05-14 Sgs Thomson Microelectronics Dispositivo a semiconduttore comprendente un circuito di comando e uno stadio di potenza a flusso di corrente verticale integrati in modo monolitico nella stessa piastrina e relativo processo di fabbricazione
US5866461A (en) * 1990-12-30 1999-02-02 Stmicroelectronics S.R.L. Method for forming an integrated emitter switching configuration using bipolar transistors
EP0709890B1 (en) * 1994-10-27 1999-09-08 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Driving circuit for electronic semiconductor devices including at least a power transistor
US5633180A (en) * 1995-06-01 1997-05-27 Harris Corporation Method of forming P-type islands over P-type buried layer
EP0780900B1 (en) * 1995-12-19 2003-04-02 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Monolithic semiconductor device having an edge structure and method for producing said structure
JP3602242B2 (ja) * 1996-02-14 2004-12-15 株式会社ルネサステクノロジ 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3663872A (en) * 1969-01-22 1972-05-16 Nippon Electric Co Integrated circuit lateral transistor
DE2131993C2 (de) * 1971-06-28 1984-10-11 Telefunken electronic GmbH, 7100 Heilbronn Verfahren zum Herstellen eines niederohmigen Anschlusses
US4203126A (en) * 1975-11-13 1980-05-13 Siliconix, Inc. CMOS structure and method utilizing retarded electric field for minimum latch-up
US4213806A (en) * 1978-10-05 1980-07-22 Analog Devices, Incorporated Forming an IC chip with buried zener diode
IT1214805B (it) * 1984-08-21 1990-01-18 Ates Componenti Elettron Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown
IT1214808B (it) * 1984-12-20 1990-01-18 Ates Componenti Elettron Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli
IT1215024B (it) * 1986-10-01 1990-01-31 Sgs Microelettronica Spa Processo per la formazione di un dispositivo monolitico a semiconduttore di alta tensione

Also Published As

Publication number Publication date
US4889822A (en) 1989-12-26
EP0307032A2 (en) 1989-03-15
DE3852362T2 (de) 1995-05-24
IT1221587B (it) 1990-07-12
DE3852362D1 (de) 1995-01-19
EP0307032B1 (en) 1994-12-07
JPH0195552A (ja) 1989-04-13
EP0307032A3 (en) 1991-03-06

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970929