IT8421113A0 - Procedimento per fabbricare transistor ad effetto di campo. - Google Patents

Procedimento per fabbricare transistor ad effetto di campo.

Info

Publication number
IT8421113A0
IT8421113A0 IT8421113A IT2111384A IT8421113A0 IT 8421113 A0 IT8421113 A0 IT 8421113A0 IT 8421113 A IT8421113 A IT 8421113A IT 2111384 A IT2111384 A IT 2111384A IT 8421113 A0 IT8421113 A0 IT 8421113A0
Authority
IT
Italy
Prior art keywords
procedure
field effect
effect transistors
manufacturing field
manufacturing
Prior art date
Application number
IT8421113A
Other languages
English (en)
Other versions
IT8421113A1 (it
IT1176216B (it
Inventor
William Thomas Lynch
Frederick Vratny
Original Assignee
American Telephone & Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph
Publication of IT8421113A0 publication Critical patent/IT8421113A0/it
Publication of IT8421113A1 publication Critical patent/IT8421113A1/it
Application granted granted Critical
Publication of IT1176216B publication Critical patent/IT1176216B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
IT21113/84A 1983-05-27 1984-05-25 Procedimento per fabbricare transistor ad effetto di campo IT1176216B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/498,897 US4453306A (en) 1983-05-27 1983-05-27 Fabrication of FETs

Publications (3)

Publication Number Publication Date
IT8421113A0 true IT8421113A0 (it) 1984-05-25
IT8421113A1 IT8421113A1 (it) 1985-11-25
IT1176216B IT1176216B (it) 1987-08-18

Family

ID=23982953

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21113/84A IT1176216B (it) 1983-05-27 1984-05-25 Procedimento per fabbricare transistor ad effetto di campo

Country Status (9)

Country Link
US (1) US4453306A (it)
KR (1) KR930001559B1 (it)
CA (1) CA1203322A (it)
DE (1) DE3419080A1 (it)
FR (1) FR2546664B1 (it)
GB (1) GB2140619B (it)
HK (1) HK53387A (it)
IT (1) IT1176216B (it)
NL (1) NL8401689A (it)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4822754A (en) * 1983-05-27 1989-04-18 American Telephone And Telegraph Company, At&T Bell Laboratories Fabrication of FETs with source and drain contacts aligned with the gate electrode
JPS60223165A (ja) * 1984-04-19 1985-11-07 Toshiba Corp 半導体装置の製造方法
US4599789A (en) * 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
JPS614240A (ja) * 1984-06-18 1986-01-10 Toshiba Corp 半導体装置の製造方法
US4628588A (en) * 1984-06-25 1986-12-16 Texas Instruments Incorporated Molybdenum-metal mask for definition and etch of oxide-encapsulated metal gate
US4577392A (en) * 1984-08-03 1986-03-25 Advanced Micro Devices, Inc. Fabrication technique for integrated circuits
US5227319A (en) * 1985-02-08 1993-07-13 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US5072275A (en) * 1986-02-28 1991-12-10 Fairchild Semiconductor Corporation Small contactless RAM cell
US5100824A (en) * 1985-04-01 1992-03-31 National Semiconductor Corporation Method of making small contactless RAM cell
US5340762A (en) * 1985-04-01 1994-08-23 Fairchild Semiconductor Corporation Method of making small contactless RAM cell
CA1258320A (en) * 1985-04-01 1989-08-08 Madhukar B. Vora Small contactless ram cell
GB2180991B (en) * 1985-08-28 1988-11-23 Mitsubishi Electric Corp Method for forming silicide electrode in semiconductor device
JPH0799738B2 (ja) * 1985-09-05 1995-10-25 三菱電機株式会社 半導体装置の製造方法
JP2537936B2 (ja) * 1986-04-23 1996-09-25 エイ・ティ・アンド・ティ・コーポレーション 半導体デバイスの製作プロセス
US4974046A (en) * 1986-07-02 1990-11-27 National Seimconductor Corporation Bipolar transistor with polysilicon stringer base contact
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
US4752590A (en) * 1986-08-20 1988-06-21 Bell Telephone Laboratories, Incorporated Method of producing SOI devices
US4826782A (en) * 1987-04-17 1989-05-02 Tektronix, Inc. Method of fabricating aLDD field-effect transistor
EP0296718A3 (en) * 1987-06-26 1990-05-02 Hewlett-Packard Company A coplanar and self-aligned contact structure
KR920000077B1 (ko) * 1987-07-28 1992-01-06 가부시키가이샤 도시바 반도체장치의 제조방법
US4755478A (en) * 1987-08-13 1988-07-05 International Business Machines Corporation Method of forming metal-strapped polysilicon gate electrode for FET device
US4844776A (en) * 1987-12-04 1989-07-04 American Telephone And Telegraph Company, At&T Bell Laboratories Method for making folded extended window field effect transistor
US4922311A (en) * 1987-12-04 1990-05-01 American Telephone And Telegraph Company Folded extended window field effect transistor
JPH01175260A (ja) * 1987-12-29 1989-07-11 Nec Corp 絶縁ゲート電界効果トランジスタの製造方法
US4859278A (en) * 1988-08-11 1989-08-22 Xerox Corporation Fabrication of high resistive loads utilizing a single level polycide process
US4945070A (en) * 1989-01-24 1990-07-31 Harris Corporation Method of making cmos with shallow source and drain junctions
US5221634A (en) * 1989-01-31 1993-06-22 Texas Instruments Incorporated Method of making semiconductor device employing self diffusion of dopant from contact member for augmenting electrical connection to doped region in substrate
US4992848A (en) * 1990-02-20 1991-02-12 At&T Bell Laboratories Self-aligned contact technology
US4980304A (en) * 1990-02-20 1990-12-25 At&T Bell Laboratories Process for fabricating a bipolar transistor with a self-aligned contact
AT404524B (de) * 1991-09-03 1998-12-28 Austria Mikrosysteme Int Verfahren zur herstellung von selbstausgerichteten, lateralen und vertikalen halbleiterbauelementen
US5461005A (en) * 1991-12-27 1995-10-24 At&T Ipm Corp. Method of forming silicide in integrated circuit manufacture
US6475911B1 (en) * 2000-08-16 2002-11-05 Micron Technology, Inc. Method of forming noble metal pattern
KR100536593B1 (ko) * 2002-12-05 2005-12-14 삼성전자주식회사 선택적인 막 제거를 위한 세정 용액 및 그 세정 용액을사용하여 실리사이드 공정에서 막을 선택적으로 제거하는방법
KR100973007B1 (ko) * 2008-01-29 2010-07-30 삼성전기주식회사 금속제품의 무전해 주석 환원 도금용 도금액 및 이를이용한 금속제품의 무전해 주석 환원 도금방법
US8723154B2 (en) * 2010-09-29 2014-05-13 Crossbar, Inc. Integration of an amorphous silicon resistive switching device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL302322A (it) * 1963-02-08
NL161306C (nl) * 1971-05-28 1980-01-15 Fujitsu Ltd Werkwijze voor de vervaardiging van veldeffecttransis- toren met geisoleerde stuurelektrode.
US4319395A (en) * 1979-06-28 1982-03-16 Motorola, Inc. Method of making self-aligned device
FR2481005A1 (fr) * 1980-04-17 1981-10-23 Western Electric Co Procede de fabrication de transistors a effet de champ a canal court
US4343082A (en) * 1980-04-17 1982-08-10 Bell Telephone Laboratories, Incorporated Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device
DE3175081D1 (en) * 1980-12-12 1986-09-11 Toshiba Kk Method of manufacturing a semiconductor device of the mis type
US4398341A (en) * 1981-09-21 1983-08-16 International Business Machines Corp. Method of fabricating a highly conductive structure

Also Published As

Publication number Publication date
US4453306A (en) 1984-06-12
GB2140619B (en) 1986-10-01
CA1203322A (en) 1986-04-15
IT8421113A1 (it) 1985-11-25
HK53387A (en) 1987-07-24
KR930001559B1 (ko) 1993-03-04
DE3419080A1 (de) 1984-11-29
GB2140619A (en) 1984-11-28
NL8401689A (nl) 1984-12-17
FR2546664A1 (fr) 1984-11-30
FR2546664B1 (fr) 1985-11-29
IT1176216B (it) 1987-08-18
KR850000807A (ko) 1985-03-09
GB8413089D0 (en) 1984-06-27

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