IT1241526B - Procedimento per la fabbricazione di condensatori per celle di memoriadel tipo dram - Google Patents

Procedimento per la fabbricazione di condensatori per celle di memoriadel tipo dram

Info

Publication number
IT1241526B
IT1241526B IT48192A IT4819290A IT1241526B IT 1241526 B IT1241526 B IT 1241526B IT 48192 A IT48192 A IT 48192A IT 4819290 A IT4819290 A IT 4819290A IT 1241526 B IT1241526 B IT 1241526B
Authority
IT
Italy
Prior art keywords
condensers
procedure
manufacture
memory cells
dram type
Prior art date
Application number
IT48192A
Other languages
English (en)
Other versions
IT9048192A0 (it
IT9048192A1 (it
Inventor
Jin-Suk Choi
Kyoung-Ha Son
Young-Chul Ahn
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of IT9048192A0 publication Critical patent/IT9048192A0/it
Publication of IT9048192A1 publication Critical patent/IT9048192A1/it
Application granted granted Critical
Publication of IT1241526B publication Critical patent/IT1241526B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/911Differential oxidation and etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
IT48192A 1990-06-21 1990-07-31 Procedimento per la fabbricazione di condensatori per celle di memoriadel tipo dram IT1241526B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR900009188 1990-06-21

Publications (3)

Publication Number Publication Date
IT9048192A0 IT9048192A0 (it) 1990-07-31
IT9048192A1 IT9048192A1 (it) 1992-01-31
IT1241526B true IT1241526B (it) 1994-01-17

Family

ID=19300367

Family Applications (1)

Application Number Title Priority Date Filing Date
IT48192A IT1241526B (it) 1990-06-21 1990-07-31 Procedimento per la fabbricazione di condensatori per celle di memoriadel tipo dram

Country Status (6)

Country Link
US (1) US5104821A (it)
JP (1) JPH0453160A (it)
DE (1) DE4024195A1 (it)
FR (1) FR2663786A1 (it)
GB (1) GB2245422A (it)
IT (1) IT1241526B (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223448A (en) * 1991-07-18 1993-06-29 Industrial Technology Research Institute Method for producing a layered capacitor structure for a dynamic random access memory device
DE19536465A1 (de) * 1995-09-29 1997-04-03 Siemens Ag Integrierbarer Kondensator und Verfahren zu seiner Herstellung
DE19536528A1 (de) * 1995-09-29 1997-04-03 Siemens Ag Integrierbarer Kondensator und Verfahren zu seiner Herstellung
US5563088A (en) * 1996-02-02 1996-10-08 Vanguard International Semiconductor Corporation Method for fabricating a stacked capacitor in a DRAM cell
US5770510A (en) * 1996-12-09 1998-06-23 Vanguard International Semiconductor Corporation Method for manufacturing a capacitor using non-conformal dielectric
TW463289B (en) * 1997-06-27 2001-11-11 Taiwan Semiconductor Mfg Method for forming annular capacitor of memory
TW331029B (en) * 1997-07-28 1998-05-01 Ti Acer Co Ltd The crown shape stack capacitor and its producing method
US6011286A (en) * 1997-10-31 2000-01-04 Texas Instruments Double stair-like capacitor structure for a DRAM cell
US5807777A (en) * 1997-11-03 1998-09-15 Texas Instruments - Acer Incorporated Method of making a double stair-like capacitor for a high density DRAM cell
US6281542B1 (en) 1998-04-14 2001-08-28 Tsmc-Acer Semiconductor Manufacturing Corp. Flower-like capacitor structure for a memory cell
TW413932B (en) 1999-03-05 2000-12-01 Nanya Plastics Corp Manufacturing method of crown-type capacitor structure
TW415084B (en) * 1999-03-05 2000-12-11 Nanya Technology Corp Fabrication method of crown-shaped capacitor structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0821682B2 (ja) * 1987-04-24 1996-03-04 株式会社日立製作所 半導体装置の製造方法
JPH0666437B2 (ja) * 1987-11-17 1994-08-24 富士通株式会社 半導体記憶装置及びその製造方法
JP2723530B2 (ja) * 1988-04-13 1998-03-09 日本電気株式会社 ダイナミック型ランダムアクセスメモリ装置の製造方法
KR910010167B1 (ko) * 1988-06-07 1991-12-17 삼성전자 주식회사 스택 캐패시터 dram셀 및 그의 제조방법
DE3918924C2 (de) * 1988-06-10 1996-03-21 Mitsubishi Electric Corp Herstellungsverfahren für eine Halbleiterspeichereinrichtung

Also Published As

Publication number Publication date
DE4024195A1 (de) 1992-01-30
GB2245422A (en) 1992-01-02
GB9016764D0 (en) 1990-09-12
JPH0453160A (ja) 1992-02-20
US5104821A (en) 1992-04-14
IT9048192A0 (it) 1990-07-31
FR2663786A1 (fr) 1991-12-27
IT9048192A1 (it) 1992-01-31

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Legal Events

Date Code Title Description
0001 Granted