ITMI910030A0 - Metodo per migliorare le caratteristiche di cancellazione elettrica di celle di memoria a porta isolata - Google Patents

Metodo per migliorare le caratteristiche di cancellazione elettrica di celle di memoria a porta isolata

Info

Publication number
ITMI910030A0
ITMI910030A0 IT91MI30A ITMI910030A ITMI910030A0 IT MI910030 A0 ITMI910030 A0 IT MI910030A0 IT 91MI30 A IT91MI30 A IT 91MI30A IT MI910030 A ITMI910030 A IT MI910030A IT MI910030 A0 ITMI910030 A0 IT MI910030A0
Authority
IT
Italy
Prior art keywords
improving
memory cells
port memory
erasing characteristics
electrical erasing
Prior art date
Application number
IT91MI30A
Other languages
English (en)
Inventor
Stefan K C Lai
Stefan Lai
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of ITMI910030A0 publication Critical patent/ITMI910030A0/it
Publication of ITMI910030A1 publication Critical patent/ITMI910030A1/it
Application granted granted Critical
Publication of IT1245208B publication Critical patent/IT1245208B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
ITMI910030A 1990-01-09 1991-01-09 Metodo per migliorare le caratteristiche di cancellazione elettrica di celle di memoria a porta isolata IT1245208B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/462,709 US5106772A (en) 1990-01-09 1990-01-09 Method for improving the electrical erase characteristics of floating gate memory cells by immediately depositing a protective polysilicon layer following growth of the tunnel or gate oxide

Publications (3)

Publication Number Publication Date
ITMI910030A0 true ITMI910030A0 (it) 1991-01-09
ITMI910030A1 ITMI910030A1 (it) 1992-07-09
IT1245208B IT1245208B (it) 1994-09-13

Family

ID=23837482

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI910030A IT1245208B (it) 1990-01-09 1991-01-09 Metodo per migliorare le caratteristiche di cancellazione elettrica di celle di memoria a porta isolata

Country Status (5)

Country Link
US (1) US5106772A (it)
JP (1) JPH04211176A (it)
KR (1) KR100189222B1 (it)
GB (1) GB2239734B (it)
IT (1) IT1245208B (it)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177028A (en) * 1991-10-22 1993-01-05 Micron Technology, Inc. Trench isolation method having a double polysilicon gate formed on mesas
US5352619A (en) * 1993-07-22 1994-10-04 United Microelectronics Corporation Method for improving erase characteristics and coupling ratios of buried bit line flash EPROM devices
US5349220A (en) * 1993-08-10 1994-09-20 United Microelectronics Corporation Flash memory cell and its operation
DE4333979A1 (de) * 1993-10-05 1995-04-13 Gold Star Electronics Nichtflüchtiger Halbleiterspeicher und Verfahren zu dessen Herstellung
JP2626523B2 (ja) * 1993-12-01 1997-07-02 日本電気株式会社 不揮発性半導体記憶装置及びその製造方法
JP3394859B2 (ja) * 1995-10-18 2003-04-07 シャープ株式会社 半導体記憶装置の製造方法
US6198114B1 (en) * 1997-10-28 2001-03-06 Stmicroelectronics, Inc. Field effect transistor having dielectrically isolated sources and drains and method for making same
US6284602B1 (en) 1999-09-20 2001-09-04 Advanced Micro Devices, Inc. Process to reduce post cycling program VT dispersion for NAND flash memory devices
US6527297B1 (en) 2000-08-30 2003-03-04 Autoliv Asp, Inc. Inflator device ignition of gas generant
JP2002134634A (ja) * 2000-10-25 2002-05-10 Nec Corp 半導体装置及びその製造方法
US6774426B2 (en) 2000-12-19 2004-08-10 Micron Technology, Inc. Flash cell with trench source-line connection
JP2003017594A (ja) * 2001-06-28 2003-01-17 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7180125B2 (en) * 2004-08-16 2007-02-20 Chih-Hsin Wang P-channel electrically alterable non-volatile memory cell
US7626864B2 (en) * 2006-04-26 2009-12-01 Chih-Hsin Wang Electrically alterable non-volatile memory cells and arrays
US7588982B2 (en) * 2006-08-29 2009-09-15 Micron Technology, Inc. Methods of forming semiconductor constructions and flash memory cells
EP2450945B1 (en) * 2010-11-08 2013-05-29 Imec Method for producing a floating gate memory structure

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3797000A (en) * 1972-12-29 1974-03-12 Ibm Non-volatile semiconductor storage device utilizing avalanche injection and extraction of stored information
US3984822A (en) * 1974-12-30 1976-10-05 Intel Corporation Double polycrystalline silicon gate memory device
NL7500550A (nl) * 1975-01-17 1976-07-20 Philips Nv Halfgeleider-geheugeninrichting.
US4115914A (en) * 1976-03-26 1978-09-26 Hughes Aircraft Company Electrically erasable non-volatile semiconductor memory
US4114255A (en) * 1976-08-16 1978-09-19 Intel Corporation Floating gate storage device and method of fabrication
US4150389A (en) * 1976-09-29 1979-04-17 Siemens Aktiengesellschaft N-channel memory field effect transistor
US4288256A (en) * 1977-12-23 1981-09-08 International Business Machines Corporation Method of making FET containing stacked gates
US4178674A (en) * 1978-03-27 1979-12-18 Intel Corporation Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor
JPS5561037A (en) * 1978-10-31 1980-05-08 Toshiba Corp Preparation of semiconductor device
EP0056195B1 (en) * 1980-12-25 1986-06-18 Fujitsu Limited Nonvolatile semiconductor memory device
US4407696A (en) * 1982-12-27 1983-10-04 Mostek Corporation Fabrication of isolation oxidation for MOS circuit
JP2515715B2 (ja) * 1984-02-24 1996-07-10 株式会社日立製作所 半導体集積回路装置の製造方法
JPH0628282B2 (ja) * 1984-09-19 1994-04-13 ソニー株式会社 半導体装置の製造方法
US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
IT1201834B (it) * 1986-07-10 1989-02-02 Sgs Microelettronica Spa Dispositivo di memoria non volatile a semiconduttore
JPS63137457A (ja) * 1986-11-28 1988-06-09 Fujitsu Ltd 半導体装置の製造方法
JP2633541B2 (ja) * 1987-01-07 1997-07-23 株式会社東芝 半導体メモリ装置の製造方法
EP0280276B1 (en) * 1987-02-27 1993-05-19 Kabushiki Kaisha Toshiba Ultraviolet erasable nonvolatile semiconductor memory device and manufacturing method therefor
US4780424A (en) * 1987-09-28 1988-10-25 Intel Corporation Process for fabricating electrically alterable floating gate memory devices
US5002898A (en) * 1989-10-19 1991-03-26 At&T Bell Laboratories Integrated-circuit device isolation
US5010028A (en) * 1989-12-29 1991-04-23 Texas Instruments Incorporated Method of making hot electron programmable, tunnel electron erasable contactless EEPROM

Also Published As

Publication number Publication date
GB2239734A (en) 1991-07-10
KR910015065A (ko) 1991-08-31
GB9026697D0 (en) 1991-01-23
KR100189222B1 (ko) 1999-07-01
JPH04211176A (ja) 1992-08-03
ITMI910030A1 (it) 1992-07-09
GB2239734B (en) 1993-11-10
US5106772A (en) 1992-04-21
IT1245208B (it) 1994-09-13

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19980127