IT1160420B - High-performance input-output controller - Google Patents

High-performance input-output controller

Info

Publication number
IT1160420B
IT1160420B IT22656/80A IT2265680A IT1160420B IT 1160420 B IT1160420 B IT 1160420B IT 22656/80 A IT22656/80 A IT 22656/80A IT 2265680 A IT2265680 A IT 2265680A IT 1160420 B IT1160420 B IT 1160420B
Authority
IT
Italy
Prior art keywords
controller
storage
host processor
data transfer
microprocessor
Prior art date
Application number
IT22656/80A
Other languages
Italian (it)
Other versions
IT8022656A0 (en
Inventor
John Monroe Dinwiddie
Boddy Joe Freeman
Timothy Jackson
William Lewis Zipoy
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/062,261 external-priority patent/US4309754A/en
Application filed by Ibm filed Critical Ibm
Publication of IT8022656A0 publication Critical patent/IT8022656A0/en
Application granted granted Critical
Publication of IT1160420B publication Critical patent/IT1160420B/en

Links

Abstract

The input/output controller includes a microprocessor for supervising data transfer between a host processor and the controller and a microprocessor I/O bus coupled to I/O units. A storage unit is located in the I/O controller for providing a data transfer interface between the microprocessor I/O bus and the I/O channel bus of the host processor. First storage accessing circuitry including the microprocessor and chip select decoder provides a data transfer path between a dual-port random access storage mechanism and an I/O unit. Second storage accessing circuitry including a direct memory access controller unit and chip select decoder supplies host processor main storage addresses to the host processor and controller storage addresses to the storage mechanism. These addresses enable transfer of data between the host processor main storage unit and the controller storage mechanism in a first data transfer mode e.g. a cycle steal mode.. More efficient and flexible data transfer are achieved where several I/O units are connected to the I/O controller. So that a high performance I/O controller is provided which is flexible and versatile in terms of the kinds and numbers of tasks it can perform and I/O units it can handle.
IT22656/80A 1979-07-30 1980-06-09 High-performance input-output controller IT1160420B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US6226379A 1979-07-30 1979-07-30
US6226279A 1979-07-30 1979-07-30
US06/062,261 US4309754A (en) 1979-07-30 1979-07-30 Data interface mechanism for interfacing bit-parallel data buses of different bit width

Publications (2)

Publication Number Publication Date
IT8022656A0 IT8022656A0 (en) 1980-06-09
IT1160420B true IT1160420B (en) 1987-03-11

Family

ID=27370240

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22656/80A IT1160420B (en) 1979-07-30 1980-06-09 High-performance input-output controller

Country Status (1)

Country Link
IT (1) IT1160420B (en)

Also Published As

Publication number Publication date
IT8022656A0 (en) 1980-06-09

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19940629