JPS6430091A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS6430091A
JPS6430091A JP62183302A JP18330287A JPS6430091A JP S6430091 A JPS6430091 A JP S6430091A JP 62183302 A JP62183302 A JP 62183302A JP 18330287 A JP18330287 A JP 18330287A JP S6430091 A JPS6430091 A JP S6430091A
Authority
JP
Japan
Prior art keywords
wdl
data
arithmetic
write data
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62183302A
Other languages
Japanese (ja)
Inventor
Mikio Yamagishi
Masaru Shibukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62183302A priority Critical patent/JPS6430091A/en
Publication of JPS6430091A publication Critical patent/JPS6430091A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the number of steps necessary for repeated processing of product sum operation or the like by simultaneously supplying new read data and an arithmetic result stored in a writing data latch to an arithmetic logical operation unit. CONSTITUTION:A write data latch (WDL) for holding write data is formed in a RAM and an input route for inputting the write data stored in the WDL to a specified address of a memory array M-ARY and an output route for outputting the write data stored in the WDL as it is to a prescribed data bus out of data buses DB-A-DB-C are formed. Thereby, the read new data and the arithmetic result stored in the WDL can be simultaneously supplied to the arithmetic logical operation unit (ALU). Consequently, the number of steps necessary for the arithmetic processing can be reduced and the processing performance of microprocessor or the like including the RAM can be improved.
JP62183302A 1987-07-24 1987-07-24 Semiconductor storage device Pending JPS6430091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183302A JPS6430091A (en) 1987-07-24 1987-07-24 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183302A JPS6430091A (en) 1987-07-24 1987-07-24 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6430091A true JPS6430091A (en) 1989-01-31

Family

ID=16133296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183302A Pending JPS6430091A (en) 1987-07-24 1987-07-24 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6430091A (en)

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