JPH0261722A - Arithmetic device - Google Patents

Abstract

PURPOSE:To increase the speed of the whole of an arithmetic device about twice with memories having the same speed by using a memory circuit dual port memory where data to be operated are stored. CONSTITUTION:In the arithmetic device having a storage circuit where data to be operated which should be inputted to its computing element and operation result data are stored, the storage circuit where data to be operated and operation result data are stored consists of a dual port memory. Data A' and A read out from a storage memory 2 of data to be operated and a dual port memory 4 are inputted to a computing element 3 at the timing shown in the figure. The computing element 3 performs the arithmetic operation at a timing C shown in the figure, and features of the dual port memory 4 are used to write the operation result at a timing B, and data for the next operation are read out simultaneously, and hereafter, the same operation is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic device, and more particularly to the configuration of a memory circuit that stores operand data and arithmetic result data.

[Prior Art] Conventionally, this type of arithmetic device has a configuration in which the input terminal side and the output terminal side of the arithmetic unit 31 are connected to the memory circuit 32 through one system of wiring (bus). -A typical conventional example is shown in FIG.

[Problems to be solved by the invention] The conventional arithmetic device described above has an arithmetic circuit and a memory circuit in one.
Because they are connected via a system bus, each individual operation can be performed repeatedly, such as reading out the data to be operated on from the memory circuit, manually inputting it to the arithmetic unit, and then writing the result of the operation to the side memory circuit. In order to complete the process, access to the memory circuit requires a total number of times to read the data to be operated on and write the result of the operation, which has the disadvantage that a vacant time 41 is created during the operation of the arithmetic unit, as shown in FIG. 4(a). there were. Furthermore, in order to operate the arithmetic unit at such a speed that no idle time occurs in the arithmetic unit, there is a drawback that the operating speed of the memory circuit must be doubled as shown in FIG. 4(b).

Furthermore, since the speed of an arithmetic unit is generally much faster than that of a memory circuit, the speed of the entire device is greatly influenced by the memory access speed. For this reason, 1. Next calculation H
1, this memory access was a major drawback.

[Differences between Komei and the conventional technology] In contrast to the above-mentioned arithmetic unit from FIT, in which the arithmetic unit and the memo +, ) circuit were connected by one line of wiring, the readout and write terminals were An independent dual-port memory circuit is used, and the input and output to the arithmetic unit are connected separately, that is, with a total of two lines of wiring, and the two are connected to the U output terminal of the dual-port memory circuit. There is a difference.

[Means for Solving the Problems] The gist of the present invention is to provide an arithmetic device having an arithmetic unit and a storage circuit for storing operand data to be input to the arithmetic unit and operation result data. The storage circuit for storing the calculation result data is configured with a dual-port memory.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an operation timing chart thereof.

1 is a block ROM that controls the operation of the arithmetic unit, and 2 is a data ROM in which operand data is stored.
; To jiRA, there is 1, and 3 is the arithmetic unit. 4 is a dual port memory for storing operand data and operation results, 5 is a write pass line, 6 and 7 are read pass lines, 8 and 9 are dual baud 1-,
It is output from the program ROMI on the read and write lines for the y4 memory 4.

Similarly, 10 is a read address line for the operated data storage ROM or RAM. Reference numeral 11 denotes a control line for determining the calculation operation of the calculation unit 3. 12 and 13 are latch circuits for performing arithmetic processing in a pipeline operation.

Data A°2 read from ROM or RAM 2 storing operand data and dual port memory 4
．． is manually inputted to the arithmetic unit 3 at the timing shown in Figure 2. The arithmetic unit 3 performs arithmetic operations at the timing shown in C in the same figure, and then writes the arithmetic results at the timing shown in B in the same figure by taking advantage of the features of the dual boat memo 4.
Data for the next calculation is read and the same operation is repeated.

[Effect of Yinmei] As explained above, in the arithmetic device of the present invention, by using a dual port memory in the memory circuit that stores the operand data and the arithmetic result data, the operating efficiency of the conventional arithmetic device can be greatly improved. This has the effect of approximately doubling the overall speed of the arithmetic unit while using a memory circuit of the same speed.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a timing chart of one embodiment, FIG. 3 is a circuit diagram of a conventional example, and FIGS. 4(a) and 4(b) are timing charts of a conventional example. l...Program ROM, 2...
- Operand data storage ROM, RAM, 3...
・ ・Arithmetic unit, 4... Dual port memory circuit, 5...
...Write bus wiring to the dual port memory 4, 6.7...Read bus wiring to the dual port memory 4, 8...Read address line written to the dual port memory 4, 9... ...Write 1 address line for dual port memory 4, 10...Address line for data ROM, RAM2, 11...Arithmetic unit operation control line, 12.13...Latch circuit, 14...Dual port memory write control line. Patent applicant: NEC Corporation

Claims (1)

[Claims] In an arithmetic device having an arithmetic unit and a memory circuit for storing operand data and operation result data to be input to the arithmetic unit, the memory circuit for storing the operand data and operation result data is a dual-board memory. An arithmetic device comprising: