JPS6435794A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS6435794A
JPS6435794A JP62192321A JP19232187A JPS6435794A JP S6435794 A JPS6435794 A JP S6435794A JP 62192321 A JP62192321 A JP 62192321A JP 19232187 A JP19232187 A JP 19232187A JP S6435794 A JPS6435794 A JP S6435794A
Authority
JP
Japan
Prior art keywords
pipeline
cell array
memory
memory cell
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62192321A
Other languages
Japanese (ja)
Inventor
Naoki Nishi
Naoya Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62192321A priority Critical patent/JPS6435794A/en
Publication of JPS6435794A publication Critical patent/JPS6435794A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To further shorten a memory cycle time by providing a latch or a register of one step or above from the input step of address data to the output step of a sense amplifier, executing a pipeline action and executing simultaneously plural memory reading and writing requests. CONSTITUTION:Registers 7-10 are pipeline registers and provided between address recorders 5 and 6 and a memory cell array 13. Thus, the reading and writing processing itself in the chip of a semiconductor memory is made into a pipeline, the processing which cannot be divided by the pipeline register is of the processing only in the memory cell array, the effect of the pipeline action is increased by placing the pipeline register of one step or above from when the input except the chip is fetched up to the inlet of the memory cell array and from the outlet of the memory cell array up to the outputting of the output except the chip and a memory cycle time can be shortened.
JP62192321A 1987-07-30 1987-07-30 Semiconductor memory Pending JPS6435794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62192321A JPS6435794A (en) 1987-07-30 1987-07-30 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62192321A JPS6435794A (en) 1987-07-30 1987-07-30 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPS6435794A true JPS6435794A (en) 1989-02-06

Family

ID=16289337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62192321A Pending JPS6435794A (en) 1987-07-30 1987-07-30 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS6435794A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892723A (en) * 1995-06-08 1999-04-06 Matsushita Electric Industrial Co., Ltd. Potential difference transmission device and semiconductor memory device using the same
CN113590200A (en) * 2021-08-03 2021-11-02 北京中科芯蕊科技有限公司 Asynchronous miniflow line controller based on SR latch

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892723A (en) * 1995-06-08 1999-04-06 Matsushita Electric Industrial Co., Ltd. Potential difference transmission device and semiconductor memory device using the same
CN113590200A (en) * 2021-08-03 2021-11-02 北京中科芯蕊科技有限公司 Asynchronous miniflow line controller based on SR latch
CN113590200B (en) * 2021-08-03 2024-01-30 北京中科芯蕊科技有限公司 Asynchronous micro-pipeline controller based on SR latch

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