IN2014DN10143A - - Google Patents

Info

Publication number
IN2014DN10143A
IN2014DN10143A IN10143DEN2014A IN2014DN10143A IN 2014DN10143 A IN2014DN10143 A IN 2014DN10143A IN 10143DEN2014 A IN10143DEN2014 A IN 10143DEN2014A IN 2014DN10143 A IN2014DN10143 A IN 2014DN10143A
Authority
IN
India
Prior art keywords
gan
wafers
substrate
ammophilic
render
Prior art date
Application number
Other languages
English (en)
Inventor
Alexander Usenko
Original Assignee
Corning Inc
Alexander Usenko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Corning Inc, Alexander Usenko filed Critical Corning Inc
Publication of IN2014DN10143A publication Critical patent/IN2014DN10143A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
IN10143DEN2014 2012-05-31 2013-05-23 IN2014DN10143A (enrdf_load_stackoverflow)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/484,542 US8796054B2 (en) 2012-05-31 2012-05-31 Gallium nitride to silicon direct wafer bonding
PCT/US2013/042380 WO2013181053A1 (en) 2012-05-31 2013-05-23 Gallium nitride to silicon direct wafer bonding

Publications (1)

Publication Number Publication Date
IN2014DN10143A true IN2014DN10143A (enrdf_load_stackoverflow) 2015-08-21

Family

ID=49669153

Family Applications (1)

Application Number Title Priority Date Filing Date
IN10143DEN2014 IN2014DN10143A (enrdf_load_stackoverflow) 2012-05-31 2013-05-23

Country Status (6)

Country Link
US (1) US8796054B2 (enrdf_load_stackoverflow)
EP (1) EP2859592B1 (enrdf_load_stackoverflow)
CN (1) CN104471726B (enrdf_load_stackoverflow)
IN (1) IN2014DN10143A (enrdf_load_stackoverflow)
TW (1) TWI597800B (enrdf_load_stackoverflow)
WO (1) WO2013181053A1 (enrdf_load_stackoverflow)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9690042B2 (en) * 2013-05-23 2017-06-27 Electronics And Telecommunications Research Institute Optical input/output device, optical electronic system including the same, and method of manufacturing the same
JP6176069B2 (ja) * 2013-11-13 2017-08-09 住友電気工業株式会社 Ｉｉｉ族窒化物複合基板およびその製造方法、積層ｉｉｉ族窒化物複合基板、ならびにｉｉｉ族窒化物半導体デバイスおよびその製造方法
CN103887379B (zh) * 2014-03-28 2017-04-19 西安神光皓瑞光电科技有限公司 用湿法腐蚀减少GaN外延缺陷的方法
FR3029352B1 (fr) 2014-11-27 2017-01-06 Soitec Silicon On Insulator Procede d'assemblage de deux substrats
DE102015103323A1 (de) * 2015-03-06 2016-09-08 Infineon Technologies Austria Ag Verfahren zum Herstellen von Halbleitervorrichtungen durch Bonden einer Halbleiterscheibe auf ein Basissubstrat, zusammengesetzter Wafer und Halbleitervorrichtung
TWI645479B (zh) * 2015-05-13 2018-12-21 財團法人工業技術研究院 貼合結構、其製造方法及晶粒結構
CN115424918A (zh) * 2022-08-10 2022-12-02 中晟鲲鹏光电半导体有限公司 一种碳化硅与氮化镓键合的超薄晶圆制作工艺
WO2025079545A1 (ja) * 2023-10-12 2025-04-17 Ａｇｃ株式会社 接合用部材および接合体

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1988109B (zh) 2005-12-21 2012-03-21 弗赖贝格化合物原料有限公司 生产自支撑iii-n层和自支撑iii-n基底的方法
JP4756418B2 (ja) 2006-02-28 2011-08-24 公立大学法人大阪府立大学 単結晶窒化ガリウム基板の製造方法
JP2008004821A (ja) * 2006-06-23 2008-01-10 Sumco Corp 貼り合わせウェーハの製造方法
US7811900B2 (en) * 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
CN101960604B (zh) * 2008-03-13 2013-07-10 S.O.I.Tec绝缘体上硅技术公司 绝缘隐埋层中有带电区的衬底
TWI492275B (zh) 2008-04-10 2015-07-11 Shinetsu Chemical Co The method of manufacturing the bonded substrate
US8692260B2 (en) 2008-09-26 2014-04-08 Soitec Method of forming a composite laser substrate
US8551862B2 (en) * 2009-01-15 2013-10-08 Shin-Etsu Chemical Co., Ltd. Method of manufacturing laminated wafer by high temperature laminating method
JP2010192872A (ja) * 2009-01-23 2010-09-02 Sumitomo Electric Ind Ltd 半導体基板の製造方法、半導体デバイスの製造方法、半導体基板および半導体デバイス
US8367519B2 (en) * 2009-12-30 2013-02-05 Memc Electronic Materials, Inc. Method for the preparation of a multi-layered crystalline structure
US8330245B2 (en) * 2010-02-25 2012-12-11 Memc Electronic Materials, Inc. Semiconductor wafers with reduced roll-off and bonded and unbonded SOI structures produced from same

Also Published As

Publication number Publication date
US20130320404A1 (en) 2013-12-05
CN104471726B (zh) 2018-01-09
EP2859592A1 (en) 2015-04-15
WO2013181053A1 (en) 2013-12-05
EP2859592B1 (en) 2018-09-26
CN104471726A (zh) 2015-03-25
EP2859592A4 (en) 2016-03-02
TW201405702A (zh) 2014-02-01
TWI597800B (zh) 2017-09-01
US8796054B2 (en) 2014-08-05

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