IN2014CN01829A - - Google Patents

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Publication number
IN2014CN01829A
IN2014CN01829A IN1829CHN2014A IN2014CN01829A IN 2014CN01829 A IN2014CN01829 A IN 2014CN01829A IN 1829CHN2014 A IN1829CHN2014 A IN 1829CHN2014A IN 2014CN01829 A IN2014CN01829 A IN 2014CN01829A
Authority
IN
India
Prior art keywords
memory cells
memory array
group
memory
cells
Prior art date
Application number
Other languages
English (en)
Inventor
Michael Thaithanh Phan
Manish Garg
David Paul Hoff
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN01829A publication Critical patent/IN2014CN01829A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
IN1829CHN2014 2011-09-30 2012-09-30 IN2014CN01829A (enrdf_load_stackoverflow)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/249,297 US8824230B2 (en) 2011-09-30 2011-09-30 Method and apparatus of reducing leakage power in multiple port SRAM memory cell
PCT/US2012/058178 WO2013049763A1 (en) 2011-09-30 2012-09-30 Method and apparatus of reducing leakage power in multiple port sram memory cell

Publications (1)

Publication Number Publication Date
IN2014CN01829A true IN2014CN01829A (enrdf_load_stackoverflow) 2015-05-29

Family

ID=47073525

Family Applications (1)

Application Number Title Priority Date Filing Date
IN1829CHN2014 IN2014CN01829A (enrdf_load_stackoverflow) 2011-09-30 2012-09-30

Country Status (7)

Country Link
US (1) US8824230B2 (enrdf_load_stackoverflow)
EP (1) EP2761621B1 (enrdf_load_stackoverflow)
JP (1) JP5914671B2 (enrdf_load_stackoverflow)
KR (1) KR101536233B1 (enrdf_load_stackoverflow)
CN (1) CN103875038B (enrdf_load_stackoverflow)
IN (1) IN2014CN01829A (enrdf_load_stackoverflow)
WO (1) WO2013049763A1 (enrdf_load_stackoverflow)

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US9442675B2 (en) 2013-05-08 2016-09-13 Qualcomm Incorporated Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods
US9588573B2 (en) 2013-10-28 2017-03-07 Globalfoundries Inc. Reduced-power trace array for a processor
US20150310901A1 (en) * 2014-04-24 2015-10-29 Qualcomm Incorporated Memory with a sleep mode
US9671855B2 (en) * 2014-06-30 2017-06-06 Micron Technology, Inc. Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation
US20160093624A1 (en) 2014-09-25 2016-03-31 Kilopass Technology, Inc. Thyristor Volatile Random Access Memory and Methods of Manufacture
US9460771B2 (en) 2014-09-25 2016-10-04 Kilopass Technology, Inc. Two-transistor thyristor SRAM circuit and methods of operation
WO2016049608A1 (en) * 2014-09-25 2016-03-31 Kilopass Technology, Inc. Power reduction in thyristor random access memory
CN106030715A (zh) * 2014-09-25 2016-10-12 克劳帕斯科技有限公司 闸流晶体管易失性随机存取存储器及制造方法
US9564441B2 (en) 2014-09-25 2017-02-07 Kilopass Technology, Inc. Two-transistor SRAM semiconductor structure and methods of fabrication
US9530482B2 (en) 2014-09-25 2016-12-27 Kilopass Technology, Inc. Methods of retaining and refreshing data in a thyristor random access memory
US9741413B2 (en) 2014-09-25 2017-08-22 Kilopass Technology, Inc. Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells
US9449669B2 (en) * 2014-09-25 2016-09-20 Kilopass Technology, Inc. Cross-coupled thyristor SRAM circuits and methods of operation
US9613968B2 (en) 2014-09-25 2017-04-04 Kilopass Technology, Inc. Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
US9496021B2 (en) 2014-09-25 2016-11-15 Kilopass Technology, Inc. Power reduction in thyristor random access memory
US9564199B2 (en) 2014-09-25 2017-02-07 Kilopass Technology, Inc. Methods of reading and writing data in a thyristor random access memory
US9384825B2 (en) * 2014-09-26 2016-07-05 Qualcomm Incorporated Multi-port memory circuits
US10431269B2 (en) * 2015-02-04 2019-10-01 Altera Corporation Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration
KR101674803B1 (ko) 2015-04-17 2016-11-22 경희대학교 산학협력단 메모리 장치 및 그 동작 방법
CN105304123B (zh) * 2015-12-04 2018-06-01 上海兆芯集成电路有限公司 静态随机存取存储器
KR101927583B1 (ko) 2016-04-21 2018-12-10 연세대학교 산학협력단 로컬 비트 라인 공유 메모리 소자 및 그 구동 방법
US9761304B1 (en) 2016-09-27 2017-09-12 International Business Machines Corporation Write-bitline control in multicore SRAM arrays
US9837143B1 (en) 2016-10-12 2017-12-05 International Business Machines Corporation NAND-based write driver for SRAM
US10998040B2 (en) * 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
KR102021601B1 (ko) * 2017-09-22 2019-09-16 경북대학교 산학협력단 초저전압 메모리 장치 및 그 동작 방법
US10762934B2 (en) * 2018-06-28 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage pathway prevention in a memory storage device
WO2020142743A1 (en) * 2019-01-05 2020-07-09 Synopsys, Inc. Enhanced read sensing margin and minimized vdd for sram cell arrays
US20190228821A1 (en) * 2019-03-29 2019-07-25 Intel Corporation Programmable High-Speed and Low-power Mode FPGA Memory with Configurable Floating Bitlines Scheme
US20240282366A1 (en) * 2021-06-18 2024-08-22 University Of Southern California Augmented memory computing: a new pathway for efficient ai computations
US11940493B1 (en) * 2022-09-16 2024-03-26 Nvidia Corp. Flexible one-hot decoding logic for clock controls

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Also Published As

Publication number Publication date
WO2013049763A1 (en) 2013-04-04
KR20140079445A (ko) 2014-06-26
EP2761621B1 (en) 2023-10-18
CN103875038A (zh) 2014-06-18
US20130083613A1 (en) 2013-04-04
US8824230B2 (en) 2014-09-02
EP2761621A1 (en) 2014-08-06
JP5914671B2 (ja) 2016-05-11
JP2014528629A (ja) 2014-10-27
KR101536233B1 (ko) 2015-07-13
CN103875038B (zh) 2017-05-03

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