IN2013MN00405A - - Google Patents

Info

Publication number
IN2013MN00405A
IN2013MN00405A IN405MUN2013A IN2013MN00405A IN 2013MN00405 A IN2013MN00405 A IN 2013MN00405A IN 405MUN2013 A IN405MUN2013 A IN 405MUN2013A IN 2013MN00405 A IN2013MN00405 A IN 2013MN00405A
Authority
IN
India
Prior art keywords
techniques
computing platform
communication
multiple processor
processor computing
Prior art date
Application number
Other languages
English (en)
Inventor
Alexei V Bourd
Colin Christopher Sharp
Garcia David Rigel Garcia
Chihong Zhang
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2013MN00405A publication Critical patent/IN2013MN00405A/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/544Buffers; Shared memory; Pipes
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/546Message passing systems or structures, e.g. queues
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/60Memory management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Image Generation (AREA)
IN405MUN2013 2010-09-20 2011-09-19 IN2013MN00405A (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US38457110P 2010-09-20 2010-09-20
US201161515182P 2011-08-04 2011-08-04
US13/235,266 US8937622B2 (en) 2010-09-20 2011-09-16 Inter-processor communication techniques in a multiple-processor computing platform
US13/235,236 US9645866B2 (en) 2010-09-20 2011-09-16 Inter-processor communication techniques in a multiple-processor computing platform
PCT/US2011/052196 WO2012040121A1 (fr) 2010-09-20 2011-09-19 Techniques de communication entre processeurs dans plate-forme informatique multiprocesseur

Publications (1)

Publication Number Publication Date
IN2013MN00405A true IN2013MN00405A (fr) 2015-05-29

Family

ID=45817338

Family Applications (1)

Application Number Title Priority Date Filing Date
IN405MUN2013 IN2013MN00405A (fr) 2010-09-20 2011-09-19

Country Status (10)

Country Link
US (3) US8937622B2 (fr)
EP (2) EP2619965A1 (fr)
JP (2) JP5815712B2 (fr)
KR (2) KR101564815B1 (fr)
CN (2) CN103109274B (fr)
BR (1) BR112013006488A2 (fr)
ES (1) ES2617303T3 (fr)
HU (1) HUE033041T2 (fr)
IN (1) IN2013MN00405A (fr)
WO (2) WO2012040122A1 (fr)

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101332840B1 (ko) * 2012-01-05 2013-11-27 서울대학교산학협력단 병렬 컴퓨팅 프레임워크 기반의 클러스터 시스템, 호스트 노드, 계산 노드 및 어플리케이션 실행 방법
US8937622B2 (en) 2010-09-20 2015-01-20 Qualcomm Incorporated Inter-processor communication techniques in a multiple-processor computing platform
US9239793B2 (en) 2011-12-13 2016-01-19 Ati Technologies Ulc Mechanism for using a GPU controller for preloading caches
US9170820B2 (en) * 2011-12-15 2015-10-27 Advanced Micro Devices, Inc. Syscall mechanism for processor to processor calls
JP5238876B2 (ja) * 2011-12-27 2013-07-17 株式会社東芝 情報処理装置及び情報処理方法
US8943516B2 (en) * 2012-05-31 2015-01-27 International Business Machines Corporation Mechanism for optimized intra-die inter-nodelet messaging communication
WO2013185015A2 (fr) * 2012-06-08 2013-12-12 Advanced Micro Devices, Inc. Système et procédé destinés à assurer un faible temps d'attente à des applications au moyen de processeurs hétérogènes
US8869176B2 (en) 2012-11-09 2014-10-21 Qualcomm Incorporated Exposing host operating system services to an auxillary processor
US20140149528A1 (en) * 2012-11-29 2014-05-29 Nvidia Corporation Mpi communication of gpu buffers
KR102030733B1 (ko) 2013-01-02 2019-10-10 삼성전자주식회사 메모리 시스템 및 이의 구동 방법
US20140208134A1 (en) * 2013-01-21 2014-07-24 Texas Instruments Incorporated Host controller interface for universal serial bus (usb) power delivery
US9086813B2 (en) * 2013-03-15 2015-07-21 Qualcomm Incorporated Method and apparatus to save and restore system memory management unit (MMU) contexts
US9563561B2 (en) * 2013-06-25 2017-02-07 Intel Corporation Initiation of cache flushes and invalidations on graphics processors
CN103353851A (zh) * 2013-07-01 2013-10-16 华为技术有限公司 一种管理任务的方法和设备
US20150149745A1 (en) * 2013-11-25 2015-05-28 Markus Eble Parallelization with controlled data sharing
JP6404347B2 (ja) * 2013-12-20 2018-10-10 インテル・コーポレーション 実行オフロード
EP3092560B1 (fr) * 2014-01-06 2019-05-08 Johnson Controls Technology Company Véhicule doté de multiples domaines d'exploitation d'interface utilisateur
US9632761B2 (en) * 2014-01-13 2017-04-25 Red Hat, Inc. Distribute workload of an application to a graphics processing unit
KR102100161B1 (ko) * 2014-02-04 2020-04-14 삼성전자주식회사 Gpu 데이터 캐싱 방법 및 그에 따른 데이터 프로세싱 시스템
US10055342B2 (en) * 2014-03-19 2018-08-21 Qualcomm Incorporated Hardware-based atomic operations for supporting inter-task communication
WO2015180667A1 (fr) * 2014-05-28 2015-12-03 Mediatek Inc. Système informatique à surdébit d'échange de données réduit et procédé d'échange de données associé
WO2016068999A1 (fr) * 2014-10-31 2016-05-06 Hewlett Packard Enterprise Development Lp Unités de traitement hétérogènes intégrées
GB2533768B (en) * 2014-12-19 2021-07-21 Advanced Risc Mach Ltd Cleaning a write-back cache
JP6338152B2 (ja) * 2015-04-16 2018-06-06 日本電信電話株式会社 通信装置、通信方法、及びプログラム
JP2016208105A (ja) * 2015-04-16 2016-12-08 日本電信電話株式会社 通信装置、通信方法、及びプログラム
US9996487B2 (en) * 2015-06-26 2018-06-12 Intel Corporation Coherent fabric interconnect for use in multiple topologies
US11226840B2 (en) 2015-10-08 2022-01-18 Shanghai Zhaoxin Semiconductor Co., Ltd. Neural network unit that interrupts processing core upon condition
US10380481B2 (en) 2015-10-08 2019-08-13 Via Alliance Semiconductor Co., Ltd. Neural network unit that performs concurrent LSTM cell calculations
US10725934B2 (en) 2015-10-08 2020-07-28 Shanghai Zhaoxin Semiconductor Co., Ltd. Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode
US11029949B2 (en) 2015-10-08 2021-06-08 Shanghai Zhaoxin Semiconductor Co., Ltd. Neural network unit
US11216720B2 (en) 2015-10-08 2022-01-04 Shanghai Zhaoxin Semiconductor Co., Ltd. Neural network unit that manages power consumption based on memory accesses per period
US10664751B2 (en) 2016-12-01 2020-05-26 Via Alliance Semiconductor Co., Ltd. Processor with memory array operable as either cache memory or neural network unit memory
US10346351B2 (en) 2015-10-08 2019-07-09 Via Alliance Semiconductor Co., Ltd. Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network LSTM cells
US11221872B2 (en) 2015-10-08 2022-01-11 Shanghai Zhaoxin Semiconductor Co., Ltd. Neural network unit that interrupts processing core upon condition
US10228911B2 (en) 2015-10-08 2019-03-12 Via Alliance Semiconductor Co., Ltd. Apparatus employing user-specified binary point fixed point arithmetic
US10776690B2 (en) 2015-10-08 2020-09-15 Via Alliance Semiconductor Co., Ltd. Neural network unit with plurality of selectable output functions
US9965417B1 (en) * 2016-01-13 2018-05-08 Xilinx, Inc. Use of interrupt memory for communication via PCIe communication fabric
KR101842764B1 (ko) * 2016-03-18 2018-03-28 연세대학교 산학협력단 하드웨어 가속기와 호스트 시스템 사이의 데이터 일관성 유지 장치 및 방법
JP6146508B1 (ja) 2016-03-31 2017-06-14 日本電気株式会社 同期処理ユニット、デバイス、システムおよび方法
KR102589298B1 (ko) * 2016-05-11 2023-10-13 삼성전자주식회사 그래픽스 프로세싱 장치 및, 그래픽스 프로세싱 장치에서 캐시 바이패스를 제어하는 방법
CN106127673B (zh) * 2016-07-19 2019-02-12 腾讯科技(深圳)有限公司 一种视频处理方法、装置及计算机设备
US10152243B2 (en) 2016-09-15 2018-12-11 Qualcomm Incorporated Managing data flow in heterogeneous computing
US10248565B2 (en) * 2016-09-19 2019-04-02 Qualcomm Incorporated Hybrid input/output coherent write
US10936533B2 (en) 2016-10-18 2021-03-02 Advanced Micro Devices, Inc. GPU remote communication with triggered operations
US10417560B2 (en) 2016-12-01 2019-09-17 Via Alliance Semiconductor Co., Ltd. Neural network unit that performs efficient 3-dimensional convolutions
US10438115B2 (en) 2016-12-01 2019-10-08 Via Alliance Semiconductor Co., Ltd. Neural network unit with memory layout to perform efficient 3-dimensional convolutions
US10430706B2 (en) 2016-12-01 2019-10-01 Via Alliance Semiconductor Co., Ltd. Processor with memory array operable as either last level cache slice or neural network unit memory
US10423876B2 (en) 2016-12-01 2019-09-24 Via Alliance Semiconductor Co., Ltd. Processor with memory array operable as either victim cache or neural network unit memory
US10395165B2 (en) 2016-12-01 2019-08-27 Via Alliance Semiconductor Co., Ltd Neural network unit with neural memory and array of neural processing units that collectively perform multi-word distance rotates of row of data received from neural memory
US10515302B2 (en) 2016-12-08 2019-12-24 Via Alliance Semiconductor Co., Ltd. Neural network unit with mixed data and weight size computation capability
KR102576707B1 (ko) 2016-12-26 2023-09-08 삼성전자주식회사 전자 시스템 및 그 동작 방법
US10586148B2 (en) 2016-12-31 2020-03-10 Via Alliance Semiconductor Co., Ltd. Neural network unit with re-shapeable memory
US10565492B2 (en) 2016-12-31 2020-02-18 Via Alliance Semiconductor Co., Ltd. Neural network unit with segmentable array width rotator
US10565494B2 (en) 2016-12-31 2020-02-18 Via Alliance Semiconductor Co., Ltd. Neural network unit with segmentable array width rotator
US10140574B2 (en) 2016-12-31 2018-11-27 Via Alliance Semiconductor Co., Ltd Neural network unit with segmentable array width rotator and re-shapeable weight memory to match segment width to provide common weights to multiple rotator segments
US10331532B2 (en) * 2017-01-19 2019-06-25 Qualcomm Incorporated Periodic non-intrusive diagnosis of lockstep systems
JP2018165913A (ja) * 2017-03-28 2018-10-25 富士通株式会社 演算処理装置、情報処理装置、及び演算処理装置の制御方法
US10503652B2 (en) * 2017-04-01 2019-12-10 Intel Corporation Sector cache for compression
US10373285B2 (en) * 2017-04-09 2019-08-06 Intel Corporation Coarse grain coherency
US10325341B2 (en) 2017-04-21 2019-06-18 Intel Corporation Handling pipeline submissions across many compute units
JP7032631B2 (ja) * 2017-07-04 2022-03-09 富士通株式会社 送受信システム、送受信システムの制御方法、及び送信装置
JP6907787B2 (ja) * 2017-07-28 2021-07-21 富士通株式会社 情報処理装置および情報処理方法
KR102403379B1 (ko) * 2017-09-12 2022-06-02 주식회사 코코링크 다중 gpu간 데이터 공유 방법
KR102384759B1 (ko) * 2017-11-13 2022-04-11 삼성전자주식회사 호스트 메모리 버퍼를 사용하기 위해 호스트 장치와 속성 정보를 공유하는 스토리지 장치 및 그것을 포함하는 전자 장치
US10303384B1 (en) * 2017-11-28 2019-05-28 Western Digital Technologies, Inc. Task readiness for queued storage tasks
KR102442921B1 (ko) 2017-12-11 2022-09-13 삼성전자주식회사 디지털 시그널 프로세서(dsp)의 태스크 관리 효율을 높일 수 있는 전자 장치
KR102533241B1 (ko) 2018-01-25 2023-05-16 삼성전자주식회사 적응적으로 캐시 일관성을 제어하도록 구성된 이종 컴퓨팅 시스템
US10671460B2 (en) 2018-02-05 2020-06-02 Micron Technology, Inc. Memory access communications through message passing interface implemented in memory systems
US10776281B2 (en) * 2018-10-04 2020-09-15 International Business Machines Corporation Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latency
US10761822B1 (en) * 2018-12-12 2020-09-01 Amazon Technologies, Inc. Synchronization of computation engines with non-blocking instructions
US10628342B1 (en) * 2018-12-20 2020-04-21 Dell Products, L.P. System and method for accelerating performance of non-volatile memory RAID stacks
CN111381958B (zh) * 2018-12-29 2022-12-09 上海寒武纪信息科技有限公司 通信装置、神经网络处理芯片、组合装置和电子设备
KR20200083048A (ko) * 2018-12-31 2020-07-08 삼성전자주식회사 폴링 시간을 예측하는 뉴럴 네트워크 시스템 및 이를 이용한 뉴럴 네트워크 모델 처리 방법
US20200342109A1 (en) * 2019-04-29 2020-10-29 Hewlett Packard Enterprise Development Lp Baseboard management controller to convey data
US11256423B2 (en) * 2019-10-14 2022-02-22 Western Digital Technologies, Inc. Efficiently identifying command readiness based on system state and data spread in multi queue depth environment
CN112764668A (zh) * 2019-11-01 2021-05-07 伊姆西Ip控股有限责任公司 扩展gpu存储器的方法、电子设备和计算机程序产品
JP2021149549A (ja) * 2020-03-19 2021-09-27 キオクシア株式会社 ストレージ装置およびアドレス変換テーブルのキャッシュ制御方法
US20210373951A1 (en) * 2020-05-28 2021-12-02 Samsung Electronics Co., Ltd. Systems and methods for composable coherent devices
US20210311897A1 (en) 2020-04-06 2021-10-07 Samsung Electronics Co., Ltd. Memory with cache-coherent interconnect
CN111897653A (zh) * 2020-07-30 2020-11-06 云知声智能科技股份有限公司 一种协同计算方法、装置、系统及介质
CN112100169B (zh) * 2020-08-05 2021-09-21 中科驭数(北京)科技有限公司 数据库交互数据编码方法及装置
CN112416851B (zh) * 2020-11-30 2023-07-18 中国人民解放军国防科技大学 一种可扩展的多核片上共享存储器
US11861758B2 (en) * 2021-03-12 2024-01-02 Nvidia Corporation Packet processing acceleration using parallel processing
CN115934385B (zh) * 2023-02-08 2023-05-23 苏州浪潮智能科技有限公司 一种多核核间通信方法、系统、设备及存储介质

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242247A (ja) 1985-08-20 1987-02-24 Fujitsu Ltd キヤツシユメモリ制御方式
JP2736352B2 (ja) 1988-11-21 1998-04-02 日本電信電話株式会社 マルチプロセッサシステムにおけるキャッシュメモリ制御方法
JPH03127146A (ja) 1989-10-12 1991-05-30 Koufu Nippon Denki Kk 情報処理装置
JP3056606B2 (ja) 1993-02-17 2000-06-26 住友重機械工業株式会社 液状放射性薬剤小分け装置
US5604909A (en) 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
JPH0950399A (ja) 1995-08-10 1997-02-18 Fujitsu Ltd 多次元空間に配列されたデータの処理に適したキャッシュメモリシステム
US5854637A (en) 1995-08-17 1998-12-29 Intel Corporation Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controller
US6088740A (en) 1997-08-05 2000-07-11 Adaptec, Inc. Command queuing system for a hardware accelerated command interpreter engine
US6212667B1 (en) * 1998-07-30 2001-04-03 International Business Machines Corporation Integrated circuit test coverage evaluation and adjustment mechanism and method
US6618759B1 (en) * 2000-01-31 2003-09-09 Hewlett-Packard Development Company, L.P. Immediate mode computer graphics command caching
US6801208B2 (en) * 2000-12-27 2004-10-05 Intel Corporation System and method for cache sharing
US7653736B2 (en) 2001-12-14 2010-01-26 Nxp B.V. Data processing system having multiple processors and a communications means in a data processing system
US6891543B2 (en) 2002-05-08 2005-05-10 Intel Corporation Method and system for optimally sharing memory between a host processor and graphics processor
US7958144B2 (en) 2002-08-30 2011-06-07 Boss Logic, Llc System and method for secure reciprocal exchange of data
KR101073479B1 (ko) 2003-05-07 2011-10-17 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 분할 프로토콜 전송 방법 및 프로세싱 시스템
US7015915B1 (en) 2003-08-12 2006-03-21 Nvidia Corporation Programming multiple chips from a command buffer
GB0319697D0 (en) 2003-08-21 2003-09-24 Falanx Microsystems As Method of and apparatus for differential encoding and decoding
TW200517825A (en) 2003-11-28 2005-06-01 First Int Computer Inc Over-clocking method used in VGA card and its application method for computer system
US7310722B2 (en) 2003-12-18 2007-12-18 Nvidia Corporation Across-thread out of order instruction dispatch in a multithreaded graphics processor
GB2409303B (en) 2003-12-18 2006-10-18 Advanced Risc Mach Ltd Inter-processor communication mechanism
US7023445B1 (en) * 2004-04-12 2006-04-04 Advanced Micro Devices, Inc. CPU and graphics unit with shared cache
US7305524B2 (en) 2004-10-08 2007-12-04 International Business Machines Corporation Snoop filter directory mechanism in coherency shared memory system
US7302528B2 (en) * 2004-11-19 2007-11-27 Intel Corporation Caching bypass
US7583268B2 (en) 2005-11-10 2009-09-01 Via Technologies, Inc. Graphics pipeline precise interrupt method and apparatus
US8212832B2 (en) 2005-12-08 2012-07-03 Ati Technologies Ulc Method and apparatus with dynamic graphics surface memory allocation
US7526634B1 (en) 2005-12-19 2009-04-28 Nvidia Corporation Counter-based delay of dependent thread group execution
US7353991B2 (en) 2006-02-21 2008-04-08 David Benjamin Esplin System and method for managing wireless point-of-sale transactions
US7814486B2 (en) * 2006-06-20 2010-10-12 Google Inc. Multi-thread runtime system
JP2008140078A (ja) 2006-11-30 2008-06-19 Toshiba Corp バスブリッジ装置、情報処理装置、およびデータ転送制御方法
JP5101128B2 (ja) 2007-02-21 2012-12-19 株式会社東芝 メモリ管理システム
US8031194B2 (en) * 2007-11-09 2011-10-04 Vivante Corporation Intelligent configurable graphics bandwidth modulator
US9035959B2 (en) * 2008-03-28 2015-05-19 Intel Corporation Technique to share information among different cache coherency domains
US8358313B2 (en) 2008-04-08 2013-01-22 Avid Technology, Inc. Framework to integrate and abstract processing of multiple hardware domains, data types and format
GB2462860B (en) 2008-08-22 2012-05-16 Advanced Risc Mach Ltd Apparatus and method for communicating between a central processing unit and a graphics processing unit
US8675000B2 (en) 2008-11-07 2014-03-18 Google, Inc. Command buffers for web-based graphics rendering
US20100123717A1 (en) 2008-11-20 2010-05-20 Via Technologies, Inc. Dynamic Scheduling in a Graphics Processor
US8589629B2 (en) * 2009-03-27 2013-11-19 Advanced Micro Devices, Inc. Method for way allocation and way locking in a cache
US9354944B2 (en) * 2009-07-27 2016-05-31 Advanced Micro Devices, Inc. Mapping processing logic having data-parallel threads across processors
US8400458B2 (en) * 2009-09-09 2013-03-19 Hewlett-Packard Development Company, L.P. Method and system for blocking data on a GPU
US8859133B2 (en) 2010-08-17 2014-10-14 GM Global Technology Operations LLC Repeating frame battery with compression joining of cell tabs to welded connection terminals
US8937622B2 (en) 2010-09-20 2015-01-20 Qualcomm Incorporated Inter-processor communication techniques in a multiple-processor computing platform

Also Published As

Publication number Publication date
KR101564815B1 (ko) 2015-10-30
EP2619666A1 (fr) 2013-07-31
US9645866B2 (en) 2017-05-09
JP5738998B2 (ja) 2015-06-24
BR112013006488A2 (pt) 2016-07-26
US20150097849A1 (en) 2015-04-09
JP5815712B2 (ja) 2015-11-17
US9626234B2 (en) 2017-04-18
US20120069035A1 (en) 2012-03-22
WO2012040122A1 (fr) 2012-03-29
KR20130094322A (ko) 2013-08-23
EP2619965A1 (fr) 2013-07-31
JP2013537993A (ja) 2013-10-07
JP2013546035A (ja) 2013-12-26
US20120069029A1 (en) 2012-03-22
KR20130060337A (ko) 2013-06-07
EP2619666B1 (fr) 2016-11-23
WO2012040121A1 (fr) 2012-03-29
CN103119912A (zh) 2013-05-22
US8937622B2 (en) 2015-01-20
HUE033041T2 (hu) 2017-11-28
ES2617303T3 (es) 2017-06-16
KR101564816B1 (ko) 2015-10-30
CN103119912B (zh) 2016-06-01
CN103109274A (zh) 2013-05-15
CN103109274B (zh) 2016-08-17

Similar Documents

Publication Publication Date Title
IN2013MN00405A (fr)
WO2014028109A3 (fr) Partage de mémoire par l'intermédiaire d'une architecture de mémoire unifiée
GB2476360B (en) Sharing virtual memory-based multi-version data between the heterogenous processors of a computer platform
WO2012044738A3 (fr) Rendu distant instantané
WO2012082589A3 (fr) Équilibrage de charge entre des processeurs à usage général et des processeurs graphiques
EP2622462A4 (fr) Systèmes d'exploitation multiples
IN2014CN04203A (fr)
WO2012044829A3 (fr) Interaction utilisateur au niveau d'applications d'environnements multiples effectuée au moyen d'un contexte graphique étendu
WO2010056511A3 (fr) Technique permettant de promouvoir une fusion d’instructions efficace
EP2467785A4 (fr) Communication entre des ordinateurs hôtes et des ressources périphériques dans un système de virtualisation d'entrée/sortie (e/s)
WO2014032031A3 (fr) Mise à l'échelle d'une instance de machine virtuelle
WO2012044828A3 (fr) Prise en charge de l'interaction utilisateur au niveau d'applications d'environnements multiples
WO2015081308A3 (fr) Virtualisation d'e/s dynamique
IN2015DN02742A (fr)
WO2009140631A3 (fr) Système informatique distribué avec système et procédé d’adresses universels
MX2012012534A (es) Objetos sub-bufer.
BR112016024424A2 (pt) renderização flexível com base em um alvo de renderização em processamento gráfico
WO2013177310A3 (fr) Délestage de calcul de serveurs en rack et procédés et des systèmes correspondants
WO2013006476A3 (fr) Épinglage dynamique de pages virtuelles partagées entre des processeurs de types différents d'une plate-forme informatique hétérogène
EP2271992A4 (fr) Procédé et système pour générer et délivrer des interruptions inter-processeur dans un processeur à noyaux multiples et dans certains systèmes à processeurs multiples à mémoire partagée
WO2010019407A3 (fr) Moteur de développement intégré pour un environnement informatique en nuage
SG159482A1 (en) Multi-mode processing module and method of use
WO2008085341A3 (fr) Procédés et systèmes pour la gestion de courant dans un système de traitement de données
WO2013106590A3 (fr) Système de données distribué basé sur l'utilisation en nuage
WO2009134927A3 (fr) Système et procédé d'application logicielle commerciale