HK113393A - Integrated multistage decoder - Google Patents

Integrated multistage decoder

Info

Publication number
HK113393A
HK113393A HK1133/93A HK113393A HK113393A HK 113393 A HK113393 A HK 113393A HK 1133/93 A HK1133/93 A HK 1133/93A HK 113393 A HK113393 A HK 113393A HK 113393 A HK113393 A HK 113393A
Authority
HK
Hong Kong
Prior art keywords
integrated multistage
multistage decoder
decoder
integrated
multistage
Prior art date
Application number
HK1133/93A
Other languages
English (en)
Inventor
Kurt Dr Prof Hoffmann
Oskar Dr Rer Nat Kowarik
Rainer Dipl-Phys Kraus
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of HK113393A publication Critical patent/HK113393A/xx

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30Accessing single arrays
    • G11C29/34Accessing multiple bits simultaneously
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
HK1133/93A 1987-03-16 1993-10-21 Integrated multistage decoder HK113393A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3708522 1987-03-16
DE3708532 1987-03-16

Publications (1)

Publication Number Publication Date
HK113393A true HK113393A (en) 1993-10-29

Family

ID=25853538

Family Applications (1)

Application Number Title Priority Date Filing Date
HK1133/93A HK113393A (en) 1987-03-16 1993-10-21 Integrated multistage decoder

Country Status (6)

Country Link
US (1) US4855621A (xx)
EP (1) EP0283908B1 (xx)
JP (1) JP2603206B2 (xx)
KR (1) KR960009244B1 (xx)
DE (1) DE3862969D1 (xx)
HK (1) HK113393A (xx)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE58903906D1 (de) * 1988-02-10 1993-05-06 Siemens Ag Redundanzdekoder eines integrierten halbleiterspeichers.
KR910003594B1 (ko) * 1988-05-13 1991-06-07 삼성전자 주식회사 스페어컬럼(column)선택방법 및 회로
FR2635600A1 (fr) * 1988-08-19 1990-02-23 Philips Nv Unite de memoire adressable a circuit de selection d'unite ameliore
KR920009059B1 (ko) * 1989-12-29 1992-10-13 삼성전자 주식회사 반도체 메모리 장치의 병렬 테스트 방법
DE69120483T2 (de) * 1990-08-17 1996-11-14 Sgs Thomson Microelectronics Halbleiter-Speicher mit unterdrücktem Testmodus-Eingang während des Strom-Einschaltens
US5072138A (en) * 1990-08-17 1991-12-10 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequential clocked access codes for test mode entry
US5072137A (en) * 1990-08-17 1991-12-10 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with a clocked access code for test mode entry
US5430678A (en) * 1990-10-02 1995-07-04 Kabushiki Kaisha Toshiba Semiconductor memory having redundant cells
JP2786020B2 (ja) * 1991-02-22 1998-08-13 日本電気アイシーマイコンシステム株式会社 半導体メモリ装置
US5631868A (en) * 1995-11-28 1997-05-20 International Business Machines Corporation Method and apparatus for testing redundant word and bit lines in a memory array
JP4235122B2 (ja) * 2004-02-06 2009-03-11 シャープ株式会社 半導体記憶装置及び半導体記憶装置のテスト方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2538373C3 (de) * 1975-08-28 1978-04-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zum Einsatz von teilfunktionsfahigen Halbleiterbausteinen in einem Speicher
US4194130A (en) * 1977-11-21 1980-03-18 Motorola, Inc. Digital predecoding system
JPS5833633B2 (ja) * 1978-08-25 1983-07-21 シャープ株式会社 Mosトランジスタ・デコ−ダ
JPS5873097A (ja) * 1981-10-27 1983-05-02 Nec Corp デコ−ダ−回路
JPS58164099A (ja) * 1982-03-25 1983-09-28 Toshiba Corp 半導体メモリ−
JPS5990291A (ja) * 1982-11-16 1984-05-24 Nec Corp メモリ
US4672240A (en) * 1983-02-07 1987-06-09 Westinghouse Electric Corp. Programmable redundancy circuit
JPS6059588A (ja) * 1983-09-12 1985-04-05 Hitachi Ltd 半導体記憶装置
US4720817A (en) * 1985-02-26 1988-01-19 Texas Instruments Incorporated Fuse selection of predecoder output
EP0198935A1 (de) * 1985-04-23 1986-10-29 Deutsche ITT Industries GmbH Elektrisch umprogrammierbarer Halbleiterspeicher mit Redundanz
US4691300A (en) * 1985-12-20 1987-09-01 Motorola, Inc. Redundant column substitution architecture with improved column access time
US4721868A (en) * 1986-09-23 1988-01-26 Advanced Micro Devices, Inc. IC input circuitry programmable for realizing multiple functions from a single input

Also Published As

Publication number Publication date
JPS63244491A (ja) 1988-10-11
US4855621A (en) 1989-08-08
KR960009244B1 (en) 1996-07-16
KR880011792A (ko) 1988-10-31
JP2603206B2 (ja) 1997-04-23
EP0283908B1 (de) 1991-05-29
DE3862969D1 (de) 1991-07-04
EP0283908A1 (de) 1988-09-28

Similar Documents

Publication Publication Date Title
EP0310057A3 (en) Decoder
GB8701731D0 (en) Pumps
EP0409205A3 (en) Viterbi decoder
GB8707001D0 (en) Compressors
EP0249982A3 (en) Decoder
GB2206648B (en) Pumps
JPS6442478A (en) Manufacture
KR960009244B1 (en) Integrated multistage decoder
ZA871566B (en) Decoder
GB8712187D0 (en) Pumps
EP0295664A3 (en) Compressor
GB2211287B (en) Ventilator
EP0289893A3 (en) Bipmos decoder circuit
GB8622680D0 (en) Decoder
GB2204122B (en) Ventilator
CS195987A1 (en) Naklapacia lezecka stena
GB8716455D0 (en) Inlet arrangements
PL267128A4 (en) Diffuser
CS133687A1 (en) Stacionarni norna stena
CS453286A1 (en) Testovaci zarizeni spiral kardiostimulacnich elektrod
ZA886100B (en) An impeller
GB8721357D0 (en) Pumping
AU98934S (en) Section
AU98932S (en) Section
AU102247S (en) Bridgins section

Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)