HK1120351A1 - Data transfer device, clock switching circuit and clock switching method - Google Patents

Data transfer device, clock switching circuit and clock switching method

Info

Publication number
HK1120351A1
HK1120351A1 HK09101164.9A HK09101164A HK1120351A1 HK 1120351 A1 HK1120351 A1 HK 1120351A1 HK 09101164 A HK09101164 A HK 09101164A HK 1120351 A1 HK1120351 A1 HK 1120351A1
Authority
HK
Hong Kong
Prior art keywords
clock switching
data transfer
transfer device
switching circuit
switching method
Prior art date
Application number
HK09101164.9A
Other languages
English (en)
Inventor
Hiroaki Arai
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Publication of HK1120351A1 publication Critical patent/HK1120351A1/xx

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
HK09101164.9A 2007-03-22 2009-02-09 Data transfer device, clock switching circuit and clock switching method HK1120351A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007074407A JP4359786B2 (ja) 2007-03-22 2007-03-22 データ伝送装置及びクロック切替回路

Publications (1)

Publication Number Publication Date
HK1120351A1 true HK1120351A1 (en) 2009-03-27

Family

ID=39908705

Family Applications (1)

Application Number Title Priority Date Filing Date
HK09101164.9A HK1120351A1 (en) 2007-03-22 2009-02-09 Data transfer device, clock switching circuit and clock switching method

Country Status (6)

Country Link
JP (1) JP4359786B2 (xx)
KR (1) KR100970351B1 (xx)
CN (1) CN101272235B (xx)
BR (1) BRPI0801097A2 (xx)
HK (1) HK1120351A1 (xx)
TW (1) TWI391827B (xx)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5401947B2 (ja) * 2008-12-01 2014-01-29 沖電気工業株式会社 クロック無瞬断切替装置およびその動作方法
US8700926B2 (en) * 2010-01-11 2014-04-15 Qualcomm Incorporated System and method of tuning a dynamic clock and voltage switching algorithm based on workload requests
CN103164363B (zh) * 2011-12-16 2018-07-17 南京中兴新软件有限责任公司 数据处理方法和装置
CN103595928B (zh) * 2013-11-19 2017-02-08 大连科迪视频技术有限公司 一种512×512的广播级超大规模3gsdi矩阵
US20200322122A1 (en) * 2017-11-22 2020-10-08 Mitsubishi Electric Corporation Data transmission device and data transmission method
KR102428498B1 (ko) 2018-10-26 2022-08-04 매그나칩 반도체 유한회사 스위칭 노이즈를 감소시킬 수 있는 수신 장치 및 이를 포함하는 전송 시스템

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2553244B1 (fr) * 1983-10-07 1988-12-30 Trt Telecom Radio Electr Dispositif de commutation avec remise en phase automatique des donnees sur 3,5 bits
KR950008665B1 (ko) * 1992-08-29 1995-08-04 한태섭 합성수지재의 입체라벨 제조방법
JPH1022821A (ja) * 1996-06-28 1998-01-23 Nec Corp 位相合わせによる系切替方式
JP3761481B2 (ja) * 2002-03-26 2006-03-29 株式会社東芝 同期回路
US6952115B1 (en) * 2003-07-03 2005-10-04 Lattice Semiconductor Corporation Programmable I/O interfaces for FPGAs and other PLDs
KR100615580B1 (ko) * 2005-07-05 2006-08-25 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 입출력 방법과이를 구비한 메모리 시스템
JP3950899B2 (ja) * 2005-08-03 2007-08-01 株式会社日立コミュニケーションテクノロジー ビット同期回路
KR100646336B1 (ko) 2005-10-10 2006-11-23 엘지전자 주식회사 데이터 샘플링 장치 및 방법과 이를 이용한 고속 직렬수신기

Also Published As

Publication number Publication date
KR20080086407A (ko) 2008-09-25
JP2008236493A (ja) 2008-10-02
CN101272235B (zh) 2012-09-19
KR100970351B1 (ko) 2010-07-15
CN101272235A (zh) 2008-09-24
BRPI0801097A2 (pt) 2008-11-18
TW200900945A (en) 2009-01-01
JP4359786B2 (ja) 2009-11-04
TWI391827B (zh) 2013-04-01

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20180320