HK1035083A1 - Sigma delta modulator-controlled phase-locked-loopcircuit and associated method. - Google Patents

Sigma delta modulator-controlled phase-locked-loopcircuit and associated method.

Info

Publication number
HK1035083A1
HK1035083A1 HK01105458A HK01105458A HK1035083A1 HK 1035083 A1 HK1035083 A1 HK 1035083A1 HK 01105458 A HK01105458 A HK 01105458A HK 01105458 A HK01105458 A HK 01105458A HK 1035083 A1 HK1035083 A1 HK 1035083A1
Authority
HK
Hong Kong
Prior art keywords
loopcircuit
locked
delta modulator
associated method
sigma delta
Prior art date
Application number
HK01105458A
Other languages
English (en)
Inventor
Hakan Bengt Eriksson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of HK1035083A1 publication Critical patent/HK1035083A1/xx

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3006—Compensating for, or preventing of, undesired influence of physical parameters
    • H03M7/3008—Compensating for, or preventing of, undesired influence of physical parameters by averaging out the errors, e.g. using dither
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2003—Modulator circuits; Transmitter circuits for continuous phase modulation
    • H04L27/2007—Modulator circuits; Transmitter circuits for continuous phase modulation in which the phase change within each symbol period is constrained
    • H04L27/2017—Modulator circuits; Transmitter circuits for continuous phase modulation in which the phase change within each symbol period is constrained in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3022—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
    • H03M7/3033—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs
    • H03M7/304—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
HK01105458A 1997-12-12 2001-08-06 Sigma delta modulator-controlled phase-locked-loopcircuit and associated method. HK1035083A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/989,864 US5986512A (en) 1997-12-12 1997-12-12 Σ-Δ modulator-controlled phase-locked-loop circuit
PCT/SE1998/002246 WO1999031807A1 (en) 1997-12-12 1998-12-08 Σδ modulator-controlled phase-locked-loop circuit and associated method

Publications (1)

Publication Number Publication Date
HK1035083A1 true HK1035083A1 (en) 2001-11-09

Family

ID=25535545

Family Applications (1)

Application Number Title Priority Date Filing Date
HK01105458A HK1035083A1 (en) 1997-12-12 2001-08-06 Sigma delta modulator-controlled phase-locked-loopcircuit and associated method.

Country Status (11)

Country Link
US (1) US5986512A (cs)
EP (1) EP1038356A1 (cs)
JP (1) JP2002509377A (cs)
KR (1) KR100535704B1 (cs)
CN (1) CN1197249C (cs)
AU (1) AU746122B2 (cs)
BR (1) BR9813555B1 (cs)
EE (1) EE200000338A (cs)
HK (1) HK1035083A1 (cs)
MY (1) MY118263A (cs)
WO (1) WO1999031807A1 (cs)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294936B1 (en) * 1998-09-28 2001-09-25 American Microsystems, Inc. Spread-spectrum modulation methods and circuit for clock generator phase-locked loop
US6717998B2 (en) 1999-12-13 2004-04-06 Matsushita Electric Industrial Co., Ltd. Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method
DE60020742T3 (de) † 1999-12-14 2009-09-17 Broadcom Corp., Irvine Frequenzteilung/vervielfachung mit minimierung des jitters
KR20020019541A (ko) * 2000-05-19 2002-03-12 롤페스 요하네스 게라투스 알베르투스 신호 생성 장치 및 위상 동기 루프 회로
US6301306B1 (en) * 2000-05-26 2001-10-09 Motorola, Inc. Method and apparatus for generating a short-range wireless data communication link
US6630868B2 (en) 2000-07-10 2003-10-07 Silicon Laboratories, Inc. Digitally-synthesized loop filter circuit particularly useful for a phase locked loop
WO2002023731A2 (en) * 2000-09-11 2002-03-21 Broadcom Corporation Methods and systems for digital dither
KR100420856B1 (ko) * 2001-01-26 2004-03-02 학교법인연세대학교 순서 비의존 투명성을 하드웨어적으로 제공해주는 병렬 렌더링 가속기
DE10115386A1 (de) * 2001-03-28 2002-10-24 Siemens Ag Noise-Shaping-Verfahren
US7042970B1 (en) * 2001-06-15 2006-05-09 Analog Devices, Inc. Phase frequency detector with adjustable offset
US6952138B2 (en) 2001-09-12 2005-10-04 Telefonaktiebolaget Lm Ericsson (Publ) Generation of a phase locked loop output signal having reduced spurious spectral components
US6674331B2 (en) * 2001-11-09 2004-01-06 Agere Systems, Inc. Method and apparatus for simplified tuning of a two-point modulated PLL
US6600378B1 (en) * 2002-01-18 2003-07-29 Nokia Corporation Fractional-N frequency synthesizer with sine wave generator
DE10205680B4 (de) * 2002-02-12 2010-06-02 Infineon Technologies Ag Ein-Punkt-Modulator mit PLL-Schaltung
JP4041323B2 (ja) * 2002-03-12 2008-01-30 松下電器産業株式会社 周波数変調装置、周波数変調方法、および、無線回路装置
US6823033B2 (en) * 2002-03-12 2004-11-23 Qualcomm Inc. ΣΔdelta modulator controlled phase locked loop with a noise shaped dither
JP4237448B2 (ja) * 2002-05-22 2009-03-11 株式会社ルネサステクノロジ 半導体装置の製造方法
US6909331B2 (en) * 2002-08-28 2005-06-21 Qualcomm Incorporated Phase locked loop having a forward gain adaptation module
CN100362743C (zh) * 2002-10-25 2008-01-16 Gct半导体公司 用于抑制锁相环电路中的噪声的系统和方法
JP3792706B2 (ja) 2002-12-26 2006-07-05 富士通株式会社 Ｐｌｌ回路のσδ変調器
AU2003217053A1 (en) 2003-04-02 2004-10-25 Christopher Julian Travis Method of establishing an oscillator clock signal
US7181180B1 (en) 2003-05-15 2007-02-20 Marvell International Ltd. Sigma delta modulated phase lock loop with phase interpolation
JP4373267B2 (ja) * 2003-07-09 2009-11-25 株式会社ルネサステクノロジ スプレッドスペクトラムクロック発生器及びそれを用いた集積回路装置
US7352249B2 (en) * 2003-10-03 2008-04-01 Analog Devices, Inc. Phase-locked loop bandwidth calibration circuit and method thereof
GB2409383B (en) * 2003-12-17 2006-06-21 Wolfson Ltd Clock synchroniser
DE102004009116B3 (de) * 2004-02-25 2005-04-28 Infineon Technologies Ag Delta-Sigma-Frequenzdiskriminator
US7098707B2 (en) * 2004-03-09 2006-08-29 Altera Corporation Highly configurable PLL architecture for programmable logic
US7706495B2 (en) * 2004-03-12 2010-04-27 Panasonic Corporation Two-point frequency modulation apparatus
US6950048B1 (en) * 2004-04-02 2005-09-27 Tektronix, Inc. Dither system for a quantizing device
US20050266805A1 (en) * 2004-05-28 2005-12-01 Jensen Henrik T Digital delta sigma modulator and applications thereof
ATE357774T1 (de) * 2004-07-01 2007-04-15 Ericsson Technology Licensing Vorrichtung mit einem sigma-delta-modulator und verfahren zur erzeugung eines quantisierten signals in einem sigma-delta modulator
WO2006002844A1 (en) * 2004-07-01 2006-01-12 Ericsson Technology Licensing Ab Apparatus comprising a sigma-delta modulator and method of generating a quantized signal in a sigma-delta modulator
US7250823B2 (en) * 2005-05-25 2007-07-31 Harris Corporation Direct digital synthesis (DDS) phase locked loop (PLL) frequency synthesizer and associated methods
WO2007004465A1 (ja) * 2005-07-04 2007-01-11 Matsushita Electric Industrial Co., Ltd. 半導体装置およびそれを用いた無線回路装置
GB0514677D0 (en) * 2005-07-18 2005-08-24 Queen Mary & Westfield College Sigma delta modulators
EP2038724A2 (en) * 2006-06-15 2009-03-25 Nxp B.V. A method of providing a clock frequency for a processor
US7570182B2 (en) * 2006-09-15 2009-08-04 Texas Instruments Incorporated Adaptive spectral noise shaping to improve time to digital converter quantization resolution using dithering
US7417510B2 (en) * 2006-09-28 2008-08-26 Silicon Laboratories Inc. Direct digital interpolative synthesis
US7764134B2 (en) * 2007-06-14 2010-07-27 Silicon Laboratories Inc. Fractional divider
US7991102B2 (en) * 2007-09-20 2011-08-02 Mediatek Inc. Signal generating apparatus and method thereof
US7911247B2 (en) * 2008-02-26 2011-03-22 Qualcomm Incorporated Delta-sigma modulator clock dithering in a fractional-N phase-locked loop
CN101572550B (zh) * 2008-04-30 2012-08-22 中芯国际集成电路制造(北京)有限公司 锁相环频率合成器及调整调制信号频率的方法
US8085097B2 (en) * 2008-05-06 2011-12-27 Hittite Microwave Corporation Integrated ramp, sweep fractional frequency synthesizer on an integrated circuit chip
US7911241B1 (en) * 2009-10-29 2011-03-22 Stmicroelectronics Design And Application Gmbh Frequency synthesizer circuit comprising a phase locked loop
US8248175B2 (en) 2010-12-30 2012-08-21 Silicon Laboratories Inc. Oscillator with external voltage control and interpolative divider in the output path
WO2012150621A1 (ja) * 2011-05-02 2012-11-08 パナソニック株式会社 周波数シンセサイザ
WO2012162886A1 (en) * 2011-06-01 2012-12-06 Huawei Technologies Co., Ltd. Spur suppression in a phase-locked loop
US8514118B2 (en) * 2011-09-23 2013-08-20 Silicon Laboratories Inc. Sigma-delta modulation with reduction of spurs using a dither signal
US9660797B2 (en) 2013-03-21 2017-05-23 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for implementing clock holdover
US9225349B2 (en) 2013-08-20 2015-12-29 Skyworks Solutions, Inc. Dither-less multi-stage noise shaping fractional-N frequency synthesizer systems and methods
US10476708B2 (en) 2016-04-13 2019-11-12 The Boeing Company Methods and apparatus to implement a signal scrambler
US10439754B2 (en) * 2016-04-13 2019-10-08 The Boeing Company Methods and apparatus to implement a third-order signal scrambler
KR102435034B1 (ko) * 2017-06-21 2022-08-23 삼성전자주식회사 디지털 위상 고정 루프 및 디지털 위상 고정 루프의 동작 방법
US10291386B2 (en) 2017-09-29 2019-05-14 Cavium, Llc Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
CN108566200A (zh) * 2018-04-27 2018-09-21 上海顺久电子科技有限公司 一种分频器控制器电路、锁相环及芯片
KR102414817B1 (ko) * 2020-05-25 2022-06-30 윈본드 일렉트로닉스 코포레이션 지연 락 루프 디바이스와 그 동작 방법
KR102392119B1 (ko) * 2021-07-21 2022-04-27 중앙대학교 산학협력단 위상 회전자를 이용한 분수 서브 샘플링 위상 고정 루프
KR102704165B1 (ko) 2022-09-08 2024-09-05 국립금오공과대학교 산학협력단 델타시그마 변조기
DE102022213918A1 (de) * 2022-12-19 2024-06-20 Robert Bosch Gesellschaft mit beschränkter Haftung Vorrichtung und Verfahren zum Reduzieren parasitärer Signalanteile eines Sigma-Delta-Modulators

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4410954A (en) * 1980-10-08 1983-10-18 Rockwell International Corporation Digital frequency synthesizer with random jittering for reducing discrete spectral spurs
GB2238434B (en) * 1989-11-22 1994-03-16 Stc Plc Frequency synthesiser
US5038117A (en) * 1990-01-23 1991-08-06 Hewlett-Packard Company Multiple-modulator fractional-N divider
US5144308A (en) * 1991-05-21 1992-09-01 At&T Bell Laboratories Idle channel tone and periodic noise suppression for sigma-delta modulators using high-level dither
US5305362A (en) * 1992-12-10 1994-04-19 Hewlett-Packard Company Spur reduction for multiple modulator based synthesis
US5808493A (en) * 1995-08-03 1998-09-15 Anritsu Corporation Rational frequency division device and frequency synthesizer using the same
US5825253A (en) * 1997-07-15 1998-10-20 Qualcomm Incorporated Phase-locked-loop with noise shaper

Also Published As

Publication number Publication date
EP1038356A1 (en) 2000-09-27
JP2002509377A (ja) 2002-03-26
EE200000338A (et) 2001-08-15
MY118263A (en) 2004-09-30
BR9813555A (pt) 2000-10-10
US5986512A (en) 1999-11-16
WO1999031807A1 (en) 1999-06-24
CN1284217A (zh) 2001-02-14
BR9813555B1 (pt) 2013-04-09
KR100535704B1 (ko) 2005-12-12
AU746122B2 (en) 2002-04-18
KR20010015841A (ko) 2001-02-26
CN1197249C (zh) 2005-04-13
AU1896099A (en) 1999-07-05

Similar Documents

Publication Publication Date Title
HK1035083A1 (en) Sigma delta modulator-controlled phase-locked-loopcircuit and associated method.
ZA981520B (en) Cavity sealing article and method.
HK1042765A1 (en) Recording device and recording method.
ZA989772B (en) Fraud prevention method and system.
AU7075298A (en) Conveying means and method
ZA9711341B (en) Method of changing the brake disc of a disc brake, and the associated disc brake.
HK1028506A1 (en) Iq modulator, and associated method
ZA973816B (en) Elastomer compositions and methods.
ZA989399B (en) Method and composition
HK1033504A1 (en) An identification arrangement and method.
EP0972915A4 (en) SILENCER AND METHOD FOR THE PRODUCTION THEREOF
EP1027464A4 (en) METHOD FOR FORGING FIELD WHEELS
ZA966071B (en) Carton engaging assembly and method.
IL124667A0 (en) Igniter assembly and method
GB9614913D0 (en) Behavior modification
ZA972061B (en) New method.
ZA9811333B (en) P. gingivalis polypeptides and nucleotides.
AU6840898A (en) Cremating method and cremator
GB2319207B (en) Casing and method for manufacturing the like
GB9708400D0 (en) Sterilising arrangement and method
ZA981346B (en) Method and arrangement for varying openings
GB2321676B (en) Bearing assembly and method
EG22228A (en) Container and coolling method
ZA989978B (en) Mixtures and methods for suppressing precipitation of chloroacetamides.
HUP9800838A3 (en) Package based on fango and method for making thereof

Legal Events

Date Code Title Description
PE Patent expired

Effective date: 20181207