HK1005492A1 - Data transfer method for a semiconductor memory and semiconductor memory to perform such a method - Google Patents
Data transfer method for a semiconductor memory and semiconductor memory to perform such a method Download PDFInfo
- Publication number
- HK1005492A1 HK1005492A1 HK98104544A HK98104544A HK1005492A1 HK 1005492 A1 HK1005492 A1 HK 1005492A1 HK 98104544 A HK98104544 A HK 98104544A HK 98104544 A HK98104544 A HK 98104544A HK 1005492 A1 HK1005492 A1 HK 1005492A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- signal
- address
- control signal
- data transmission
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
- G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Credit Cards Or The Like (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4114744 | 1991-05-06 | ||
| DE4114744A DE4114744C1 (enExample) | 1991-05-06 | 1991-05-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| HK1005492A1 true HK1005492A1 (en) | 1999-01-08 |
| HK1005492B HK1005492B (en) | 1999-01-08 |
Family
ID=
Also Published As
| Publication number | Publication date |
|---|---|
| KR100292552B1 (ko) | 2001-06-01 |
| ATE161999T1 (de) | 1998-01-15 |
| EP0513611A3 (enExample) | 1995-05-17 |
| JP3316001B2 (ja) | 2002-08-19 |
| EP0513611A2 (de) | 1992-11-19 |
| EP0513611B1 (de) | 1998-01-07 |
| JPH05151768A (ja) | 1993-06-18 |
| KR920022290A (ko) | 1992-12-19 |
| DE59209095D1 (de) | 1998-02-12 |
| US5357469A (en) | 1994-10-18 |
| DE4114744C1 (enExample) | 1992-05-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PC | Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee) |