GB9418753D0 - Process circuitry - Google Patents

Process circuitry

Info

Publication number
GB9418753D0
GB9418753D0 GB9418753A GB9418753A GB9418753D0 GB 9418753 D0 GB9418753 D0 GB 9418753D0 GB 9418753 A GB9418753 A GB 9418753A GB 9418753 A GB9418753 A GB 9418753A GB 9418753 D0 GB9418753 D0 GB 9418753D0
Authority
GB
United Kingdom
Prior art keywords
bus
control unit
access
processors
process circuitry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB9418753A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IONICA L3 Ltd
Original Assignee
IONICA L3 Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IONICA L3 Ltd filed Critical IONICA L3 Ltd
Priority to GB9418753A priority Critical patent/GB9418753D0/en
Publication of GB9418753D0 publication Critical patent/GB9418753D0/en
Priority to IN1004CA1995 priority patent/IN184524B/en
Priority to IL11514795A priority patent/IL115147A/xx
Priority to MX9701974A priority patent/MX9701974A/es
Priority to ES95931282T priority patent/ES2127554T3/es
Priority to EP95931282A priority patent/EP0781433B1/en
Priority to AU34776/95A priority patent/AU3477695A/en
Priority to BR9509071A priority patent/BR9509071A/pt
Priority to AT95931282T priority patent/ATE174139T1/de
Priority to FI971093A priority patent/FI971093A7/fi
Priority to DE69506427T priority patent/DE69506427T2/de
Priority to PCT/GB1995/002130 priority patent/WO1996008774A1/en
Priority to JP8509978A priority patent/JPH10505925A/ja
Priority to ZA957740A priority patent/ZA957740B/xx
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
  • Surgical Instruments (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Chemical Or Physical Treatment Of Fibers (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Orthopedics, Nursing, And Contraception (AREA)
  • Information Transfer Systems (AREA)
GB9418753A 1994-09-16 1994-09-16 Process circuitry Pending GB9418753D0 (en)

Priority Applications (14)

Application Number Priority Date Filing Date Title
GB9418753A GB9418753D0 (en) 1994-09-16 1994-09-16 Process circuitry
IN1004CA1995 IN184524B (enExample) 1994-09-16 1995-08-24
IL11514795A IL115147A (en) 1994-09-16 1995-09-01 Processing circuitry and a method of assigning a common bus to a plurality of processors
JP8509978A JPH10505925A (ja) 1994-09-16 1995-09-08 Ｄｓｐプロセッサのためのバス割当てシステム
AU34776/95A AU3477695A (en) 1994-09-16 1995-09-08 Bus assignment system for dsp processors
ES95931282T ES2127554T3 (es) 1994-09-16 1995-09-08 Sistema de asignacion de bus para procesadores de señales digitales.
EP95931282A EP0781433B1 (en) 1994-09-16 1995-09-08 Bus assignment system for dsp processors
MX9701974A MX9701974A (es) 1994-09-16 1995-09-08 Sistema de asignacion de barra comun para procesadores dsp.
BR9509071A BR9509071A (pt) 1994-09-16 1995-09-08 Sistema de atribuição de barramento para processadores de dsp
AT95931282T ATE174139T1 (de) 1994-09-16 1995-09-08 Buszuweisungssystem für digitalsignalprozessoren
FI971093A FI971093A7 (fi) 1994-09-16 1995-09-08 Väylänluovutusjärjestelmä DSP-prosessoreille
DE69506427T DE69506427T2 (de) 1994-09-16 1995-09-08 Buszuweisungssystem für digitalsignalprozessoren
PCT/GB1995/002130 WO1996008774A1 (en) 1994-09-16 1995-09-08 Bus assignment system for dsp processors
ZA957740A ZA957740B (en) 1994-09-16 1995-09-14 Processing circuitry

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9418753A GB9418753D0 (en) 1994-09-16 1994-09-16 Process circuitry

Publications (1)

Publication Number Publication Date
GB9418753D0 true GB9418753D0 (en) 1994-11-02

Family

ID=10761486

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9418753A Pending GB9418753D0 (en) 1994-09-16 1994-09-16 Process circuitry

Country Status (14)

Country Link
EP (1) EP0781433B1 (enExample)
JP (1) JPH10505925A (enExample)
AT (1) ATE174139T1 (enExample)
AU (1) AU3477695A (enExample)
BR (1) BR9509071A (enExample)
DE (1) DE69506427T2 (enExample)
ES (1) ES2127554T3 (enExample)
FI (1) FI971093A7 (enExample)
GB (1) GB9418753D0 (enExample)
IL (1) IL115147A (enExample)
IN (1) IN184524B (enExample)
MX (1) MX9701974A (enExample)
WO (1) WO1996008774A1 (enExample)
ZA (1) ZA957740B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2263951C2 (ru) * 2004-02-02 2005-11-10 Огородник Дмитрий Викторович Способ обработки цифровых данных в запоминающем устройстве и запоминающее устройство для осуществления способа
JP5130754B2 (ja) * 2007-03-15 2013-01-30 富士通セミコンダクター株式会社 半導体集積回路及びメモリシステム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4837736A (en) * 1987-05-01 1989-06-06 Digital Equipment Corporation Backplane bus with default control
CA2021826A1 (en) * 1989-10-23 1991-04-24 Darryl Edmond Judice Delay logic for preventing cpu lockout from bus ownership
SE9203016L (sv) * 1992-10-14 1994-04-15 Ericsson Telefon Ab L M Signalbehandlingssystem med delat dataminne
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus

Also Published As

Publication number Publication date
DE69506427T2 (de) 1999-08-05
WO1996008774A1 (en) 1996-03-21
MX9701974A (es) 1998-02-28
FI971093A0 (fi) 1997-03-14
IL115147A (en) 1999-09-22
FI971093L (fi) 1997-03-14
JPH10505925A (ja) 1998-06-09
ATE174139T1 (de) 1998-12-15
FI971093A7 (fi) 1997-03-14
ES2127554T3 (es) 1999-04-16
EP0781433A1 (en) 1997-07-02
BR9509071A (pt) 1997-12-23
ZA957740B (en) 1996-05-06
IL115147A0 (en) 1995-12-31
DE69506427D1 (de) 1999-01-14
EP0781433B1 (en) 1998-12-02
IN184524B (enExample) 2000-09-02
AU3477695A (en) 1996-03-29

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Legal Events

Date Code Title Description
730A Proceeding under section 30 patents act 1977