ATE175285T1 - Chipschnittstellenanordnung - Google Patents

Chipschnittstellenanordnung

Info

Publication number
ATE175285T1
ATE175285T1 AT91904714T AT91904714T ATE175285T1 AT E175285 T1 ATE175285 T1 AT E175285T1 AT 91904714 T AT91904714 T AT 91904714T AT 91904714 T AT91904714 T AT 91904714T AT E175285 T1 ATE175285 T1 AT E175285T1
Authority
AT
Austria
Prior art keywords
remote
data bus
chip device
mode
protocol
Prior art date
Application number
AT91904714T
Other languages
English (en)
Inventor
Craig A Schauss
Donald E Neumann
Dennis A Bielawski
Original Assignee
Gen Dynamics Land Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Dynamics Land Systems Inc filed Critical Gen Dynamics Land Systems Inc
Application granted granted Critical
Publication of ATE175285T1 publication Critical patent/ATE175285T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Information Transfer Systems (AREA)
  • Bipolar Transistors (AREA)
  • Computer And Data Communications (AREA)
  • Surgical Instruments (AREA)
  • Magnetic Heads (AREA)
  • Small-Scale Networks (AREA)
  • Semiconductor Lasers (AREA)
  • Particle Formation And Scattering Control In Inkjet Printers (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)
AT91904714T 1990-02-07 1991-02-05 Chipschnittstellenanordnung ATE175285T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47660790A 1990-02-07 1990-02-07
US07/645,901 US5181201A (en) 1990-02-07 1991-01-30 Interface chip device

Publications (1)

Publication Number Publication Date
ATE175285T1 true ATE175285T1 (de) 1999-01-15

Family

ID=27045224

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91904714T ATE175285T1 (de) 1990-02-07 1991-02-05 Chipschnittstellenanordnung

Country Status (8)

Country Link
US (1) US5181201A (de)
EP (1) EP0514477B1 (de)
JP (1) JP2540405B2 (de)
AT (1) ATE175285T1 (de)
CA (1) CA2074073C (de)
DE (1) DE69130703T2 (de)
IL (1) IL97187A (de)
WO (1) WO1991012570A1 (de)

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US5260970A (en) * 1991-06-27 1993-11-09 Hewlett-Packard Company Protocol analyzer pod for the ISDN U-interface
TW234228B (de) * 1992-05-28 1994-11-11 Motorola Inc
US5490254A (en) * 1992-11-04 1996-02-06 United Technologies Corporation MIL-STD-1553 interface device having autonomous operation in all modes
US5325359A (en) * 1992-11-04 1994-06-28 United Technologies Corporation MIL-STD-1553 interface device having concurrent remote terminal and monitor terminal operation
US5367641A (en) * 1992-11-04 1994-11-22 United Technologies Corporation MIL-STD-1553 interface device having a bus controller minor frame timer
US5619681A (en) * 1992-11-23 1997-04-08 Zilog, Inc. Delayed FIFO status for serial shift emulation
US5535400A (en) * 1994-01-28 1996-07-09 Compaq Computer Corporation SCSI disk drive power down apparatus
US6434638B1 (en) * 1994-12-09 2002-08-13 International Business Machines Corporation Arbitration protocol for peer-to-peer communication in synchronous systems
US5771356A (en) * 1995-01-04 1998-06-23 Cirrus Logic, Inc. Apparatus for controlling FIFO buffer data transfer by monitoring bus status and FIFO buffer thresholds
US5999742A (en) * 1995-01-26 1999-12-07 Zilog, Inc. Dual latch data transfer pacing logic using a timer to maintain a data transfer interval
US5721737A (en) * 1995-05-09 1998-02-24 Smc Pneumatics, Inc. Serial transmission system for controlling a network of I/O devices
US5708852A (en) * 1995-08-01 1998-01-13 International Business Machines Corporation Apparatus for serial port with pattern generation using state machine for controlling the removing of start and stop bits from serial bit data stream
US6324592B1 (en) * 1997-02-25 2001-11-27 Keystone Aerospace Apparatus and method for a mobile computer architecture and input/output management system
US6076160A (en) * 1997-11-20 2000-06-13 Advanced Micro Devices, Inc. Hardware-based system for enabling data transfers between a CPU and chip set logic of a computer system on both edges of bus clock signal
US5966379A (en) * 1998-02-17 1999-10-12 Square D Company Multiplex extender for discrete I/O devices on a time division network
US6195768B1 (en) * 1998-12-16 2001-02-27 Samuel I. Green System and method for monitoring high speed data bus
US7206833B1 (en) 1999-09-30 2007-04-17 Intel Corporation Platform independent alert detection and management
US7318089B1 (en) * 1999-09-30 2008-01-08 Intel Corporation Method and apparatus for performing network-based control functions on an alert-enabled managed client
US6922722B1 (en) 1999-09-30 2005-07-26 Intel Corporation Method and apparatus for dynamic network configuration of an alert-based client
US20020112070A1 (en) * 2000-12-08 2002-08-15 The Boeing Company Network controller for digitally controlling remote devices via a common bus
US7170179B1 (en) 2002-04-29 2007-01-30 Cypress Semiconductor Corp. Chip select method through double bonding
US7437261B2 (en) * 2003-02-14 2008-10-14 Advantest Corporation Method and apparatus for testing integrated circuits
US7430486B2 (en) * 2004-05-22 2008-09-30 Advantest America R&D Center, Inc. Datalog support in a modular test system
US7451301B2 (en) * 2005-03-30 2008-11-11 Intel Corporation OS independent device management methods and apparatuses having a map providing codes for various activations of keys
US7477176B2 (en) * 2005-07-28 2009-01-13 International Business Machines Corporation Method and apparatus for generating multiple analog signals using a single microcontroller output pin
US7765356B2 (en) * 2006-04-11 2010-07-27 Raytheon Company System for modifying data in a bus buffer
US20070300051A1 (en) * 2006-06-26 2007-12-27 Rothman Michael A Out of band asset management
JP2016092445A (ja) * 2014-10-29 2016-05-23 株式会社リコー シリアル通信システム
DE102015016775A1 (de) * 2015-12-23 2017-06-29 Audi Ag Verfahren zum Betreiben einer Sensoranordnung für einen Fluidtank eines Kraftfahrzeugs sowie entsprechende Sensoranordnung
CN110188054B (zh) * 2019-05-27 2023-10-27 中国航空无线电电子研究所 1553总线网络产品
US12105657B2 (en) * 2020-12-24 2024-10-01 Intel Corporation User signals for data transmission over a bus interface protocol
CN115481078A (zh) * 2021-05-31 2022-12-16 西安紫光国芯半导体有限公司 主从式通讯系统及方法
CN114120619B (zh) * 2021-11-12 2023-10-10 天津朗泽科技有限公司 用于检测无线电遥控装置的匹配关系的装置及其方法
CN115550098B (zh) * 2022-09-16 2023-05-05 哈尔滨工业大学 基于MiniVPX构架的ARINC429总线通信组件及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4136400A (en) * 1977-08-08 1979-01-23 Rockwell International Corporation Micro-programmable data terminal
US4471489A (en) * 1981-03-19 1984-09-11 General Datacomm Industries, Inc. Automatic answer/originate mode selection in modem
US4683530A (en) * 1984-04-10 1987-07-28 Telemecanique Electrique Serial information transfer protocol
AU591057B2 (en) * 1984-06-01 1989-11-30 Digital Equipment Corporation Local area network for digital data processing system
CA1265255A (en) * 1986-07-31 1990-01-30 John Polkinghorne Application specific integrated circuit
DE3730468A1 (de) * 1987-09-08 1989-03-16 Bergmann Kabelwerke Ag Bordnetz fuer kraftfahrzeuge und verfahren zum betrieb des bordnetzes

Also Published As

Publication number Publication date
CA2074073C (en) 1997-02-04
JP2540405B2 (ja) 1996-10-02
EP0514477A4 (en) 1993-10-20
IL97187A0 (en) 1992-05-25
EP0514477A1 (de) 1992-11-25
US5181201A (en) 1993-01-19
EP0514477B1 (de) 1998-12-30
DE69130703D1 (de) 1999-02-11
CA2074073A1 (en) 1991-08-08
WO1991012570A1 (en) 1991-08-22
DE69130703T2 (de) 1999-09-30
JPH06502029A (ja) 1994-03-03
IL97187A (en) 1994-05-30

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Legal Events

Date Code Title Description
EELA Cancelled due to lapse of time