ES2127554T3 - Sistema de asignacion de bus para procesadores de señales digitales. - Google Patents

Sistema de asignacion de bus para procesadores de señales digitales.

Info

Publication number
ES2127554T3
ES2127554T3 ES95931282T ES95931282T ES2127554T3 ES 2127554 T3 ES2127554 T3 ES 2127554T3 ES 95931282 T ES95931282 T ES 95931282T ES 95931282 T ES95931282 T ES 95931282T ES 2127554 T3 ES2127554 T3 ES 2127554T3
Authority
ES
Spain
Prior art keywords
digital signal
signal processors
bus
assignment system
bus assignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES95931282T
Other languages
English (en)
Inventor
David John Spreadbury
Clive Russell Irving
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ionica International Ltd
Original Assignee
Ionica International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ionica International Ltd filed Critical Ionica International Ltd
Application granted granted Critical
Publication of ES2127554T3 publication Critical patent/ES2127554T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)
  • Surgical Instruments (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Chemical Or Physical Treatment Of Fibers (AREA)

Abstract

TRES PROCESADORES DSP REQUIEREN SELECTIVAMENTE EL ACCESO A UNA FUENTE COMPARTIDA, TAL COMO UNA MEMORIA EXTERNA, A TRAVES DE UN BUS DE COMUNICACION COMUN. UNA UNIDAD DE CONTROL CONTROLA LA ASIGNACION DEL BUS A LOS PROCESADORES PARA PERMITIR ESTE ACCESO. EL BUS ES ASIGNADO POR DEFECTO A LA UNIDAD DE CONTROL EN LUGAR DE A UN PROCESADOR.
ES95931282T 1994-09-16 1995-09-08 Sistema de asignacion de bus para procesadores de señales digitales. Expired - Lifetime ES2127554T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9418753A GB9418753D0 (en) 1994-09-16 1994-09-16 Process circuitry

Publications (1)

Publication Number Publication Date
ES2127554T3 true ES2127554T3 (es) 1999-04-16

Family

ID=10761486

Family Applications (1)

Application Number Title Priority Date Filing Date
ES95931282T Expired - Lifetime ES2127554T3 (es) 1994-09-16 1995-09-08 Sistema de asignacion de bus para procesadores de señales digitales.

Country Status (14)

Country Link
EP (1) EP0781433B1 (es)
JP (1) JPH10505925A (es)
AT (1) ATE174139T1 (es)
AU (1) AU3477695A (es)
BR (1) BR9509071A (es)
DE (1) DE69506427T2 (es)
ES (1) ES2127554T3 (es)
FI (1) FI971093A (es)
GB (1) GB9418753D0 (es)
IL (1) IL115147A (es)
IN (1) IN184524B (es)
MX (1) MX9701974A (es)
WO (1) WO1996008774A1 (es)
ZA (1) ZA957740B (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5130754B2 (ja) * 2007-03-15 2013-01-30 富士通セミコンダクター株式会社 半導体集積回路及びメモリシステム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4837736A (en) * 1987-05-01 1989-06-06 Digital Equipment Corporation Backplane bus with default control
CA2021826A1 (en) * 1989-10-23 1991-04-24 Darryl Edmond Judice Delay logic for preventing cpu lockout from bus ownership
SE9203016L (sv) * 1992-10-14 1994-04-15 Ericsson Telefon Ab L M Signalbehandlingssystem med delat dataminne
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus

Also Published As

Publication number Publication date
FI971093A0 (fi) 1997-03-14
MX9701974A (es) 1998-02-28
EP0781433A1 (en) 1997-07-02
IN184524B (es) 2000-09-02
DE69506427D1 (de) 1999-01-14
ATE174139T1 (de) 1998-12-15
IL115147A (en) 1999-09-22
JPH10505925A (ja) 1998-06-09
DE69506427T2 (de) 1999-08-05
AU3477695A (en) 1996-03-29
WO1996008774A1 (en) 1996-03-21
GB9418753D0 (en) 1994-11-02
FI971093A (fi) 1997-03-14
EP0781433B1 (en) 1998-12-02
ZA957740B (en) 1996-05-06
IL115147A0 (en) 1995-12-31
BR9509071A (pt) 1997-12-23

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