ZA957740B - Processing circuitry - Google Patents

Processing circuitry

Info

Publication number
ZA957740B
ZA957740B ZA957740A ZA957740A ZA957740B ZA 957740 B ZA957740 B ZA 957740B ZA 957740 A ZA957740 A ZA 957740A ZA 957740 A ZA957740 A ZA 957740A ZA 957740 B ZA957740 B ZA 957740B
Authority
ZA
South Africa
Prior art keywords
bus
processing circuitry
control unit
access
processors
Prior art date
Application number
ZA957740A
Other languages
English (en)
Inventor
David John Spreadbury
Clive Russell Irving
Original Assignee
Ionica Int Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ionica Int Ltd filed Critical Ionica Int Ltd
Publication of ZA957740B publication Critical patent/ZA957740B/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)
  • Chemical Or Physical Treatment Of Fibers (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Surgical Instruments (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
ZA957740A 1994-09-16 1995-09-14 Processing circuitry ZA957740B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9418753A GB9418753D0 (en) 1994-09-16 1994-09-16 Process circuitry

Publications (1)

Publication Number Publication Date
ZA957740B true ZA957740B (en) 1996-05-06

Family

ID=10761486

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA957740A ZA957740B (en) 1994-09-16 1995-09-14 Processing circuitry

Country Status (14)

Country Link
EP (1) EP0781433B1 (es)
JP (1) JPH10505925A (es)
AT (1) ATE174139T1 (es)
AU (1) AU3477695A (es)
BR (1) BR9509071A (es)
DE (1) DE69506427T2 (es)
ES (1) ES2127554T3 (es)
FI (1) FI971093A (es)
GB (1) GB9418753D0 (es)
IL (1) IL115147A (es)
IN (1) IN184524B (es)
MX (1) MX9701974A (es)
WO (1) WO1996008774A1 (es)
ZA (1) ZA957740B (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5130754B2 (ja) * 2007-03-15 2013-01-30 富士通セミコンダクター株式会社 半導体集積回路及びメモリシステム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4837736A (en) * 1987-05-01 1989-06-06 Digital Equipment Corporation Backplane bus with default control
CA2021826A1 (en) * 1989-10-23 1991-04-24 Darryl Edmond Judice Delay logic for preventing cpu lockout from bus ownership
SE9203016L (sv) * 1992-10-14 1994-04-15 Ericsson Telefon Ab L M Signalbehandlingssystem med delat dataminne
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus

Also Published As

Publication number Publication date
FI971093A0 (fi) 1997-03-14
AU3477695A (en) 1996-03-29
JPH10505925A (ja) 1998-06-09
IL115147A0 (en) 1995-12-31
MX9701974A (es) 1998-02-28
ES2127554T3 (es) 1999-04-16
FI971093A (fi) 1997-03-14
EP0781433B1 (en) 1998-12-02
EP0781433A1 (en) 1997-07-02
IN184524B (es) 2000-09-02
GB9418753D0 (en) 1994-11-02
ATE174139T1 (de) 1998-12-15
WO1996008774A1 (en) 1996-03-21
DE69506427T2 (de) 1999-08-05
DE69506427D1 (de) 1999-01-14
IL115147A (en) 1999-09-22
BR9509071A (pt) 1997-12-23

Similar Documents

Publication Publication Date Title
DE69130703D1 (de) Chipschnittstellenanordnung
EP0653868A3 (en) Source access control system.
TR199801350T2 (xx) Yeni sikloalkil ikameli imidazoller.
EP0458104A3 (en) Power controller for multiprocessor computing system having shared input/output devices
ATE90090T1 (de) Triazole als schimmelhemmende mittel.
GB9502864D0 (en) Cryptographic reduced instruction set processor
NL7901813A (nl) Witbalansregelstelsel.
MY119755A (en) Dynamic de-registering of devices in system with multiple communication protocols
DK0613258T3 (da) Effektstyrende arrangement for duplextransmission
ATE36763T1 (de) Mikroprozessorsystem zur steuerung von arbeitsablaeufen.
ZA957740B (en) Processing circuitry
MXPA02012940A (es) Sistema y procedimiento para dirigir una unidad de procesamiento central de un aparato con multiples dispositivos y aparato correspondiente.
ES8502273A1 (es) Un controlador de sistema informatico.
JPS5334429A (en) Memory control system
DE69119105D1 (de) Weissabgleich-Steuersystem
TW362179B (en) Method and arrangement for transmitting system-specific data in a synchronous microprocessor system
JPS6460114A (en) Data arithmetic unit
GB9028179D0 (en) Multiple processor control system having shared memory communication
HK23396A (en) Direct control facility for multiprocessor network
JPS53123008A (en) Addressing system for memory
BR7100456U (pt) Disposicao em carrinho de mao domestico
WO1999031928A3 (en) An atm cell processor
RU98104914A (ru) Устройство для синтеза множественных данных импульсно-кодовой модуляции
JPS6461149A (en) Overload control system for packet exchange
JPS56146392A (en) Time-division switchboard control system