JPS53123008A - Addressing system for memory - Google Patents

Addressing system for memory

Info

Publication number
JPS53123008A
JPS53123008A JP3773277A JP3773277A JPS53123008A JP S53123008 A JPS53123008 A JP S53123008A JP 3773277 A JP3773277 A JP 3773277A JP 3773277 A JP3773277 A JP 3773277A JP S53123008 A JPS53123008 A JP S53123008A
Authority
JP
Japan
Prior art keywords
memory
addressing system
simplify
cpu
enabling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3773277A
Other languages
Japanese (ja)
Inventor
Nobuaki Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3773277A priority Critical patent/JPS53123008A/en
Publication of JPS53123008A publication Critical patent/JPS53123008A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54533—Configuration data, translation, passwords, databases

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To simplify an equipment with the need for switching memory banks eliminated increasing the capacity of the program memory which can be assigned directly by an instruction, by enabling an electronic exchange to assign addresses by output instructions of CPU.
JP3773277A 1977-04-01 1977-04-01 Addressing system for memory Pending JPS53123008A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3773277A JPS53123008A (en) 1977-04-01 1977-04-01 Addressing system for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3773277A JPS53123008A (en) 1977-04-01 1977-04-01 Addressing system for memory

Publications (1)

Publication Number Publication Date
JPS53123008A true JPS53123008A (en) 1978-10-27

Family

ID=12505653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3773277A Pending JPS53123008A (en) 1977-04-01 1977-04-01 Addressing system for memory

Country Status (1)

Country Link
JP (1) JPS53123008A (en)

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