GB2603345B - Interconnection with side connection to substrate - Google Patents

Interconnection with side connection to substrate Download PDF

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Publication number
GB2603345B
GB2603345B GB2204022.4A GB202204022A GB2603345B GB 2603345 B GB2603345 B GB 2603345B GB 202204022 A GB202204022 A GB 202204022A GB 2603345 B GB2603345 B GB 2603345B
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GB
United Kingdom
Prior art keywords
interconnection
substrate
side connection
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB2204022.4A
Other languages
English (en)
Other versions
GB2603345A (en
GB202204022D0 (en
Inventor
Miyazawa Risa
Watanabe Takahito
Mori Hiroyuki
Okamoto Keishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB202204022D0 publication Critical patent/GB202204022D0/en
Publication of GB2603345A publication Critical patent/GB2603345A/en
Application granted granted Critical
Publication of GB2603345B publication Critical patent/GB2603345B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/616—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips
    • H10W70/618—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips the bridge chips being embedded in the package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
GB2204022.4A 2019-09-27 2020-08-26 Interconnection with side connection to substrate Active GB2603345B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/585,299 US11264314B2 (en) 2019-09-27 2019-09-27 Interconnection with side connection to substrate
PCT/IB2020/057965 WO2021059052A1 (en) 2019-09-27 2020-08-26 Interconnection with side connection to substrate

Publications (3)

Publication Number Publication Date
GB202204022D0 GB202204022D0 (en) 2022-05-04
GB2603345A GB2603345A (en) 2022-08-03
GB2603345B true GB2603345B (en) 2024-05-08

Family

ID=75161694

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2204022.4A Active GB2603345B (en) 2019-09-27 2020-08-26 Interconnection with side connection to substrate

Country Status (6)

Country Link
US (1) US11264314B2 (enExample)
JP (1) JP7617906B2 (enExample)
CN (1) CN114342072B (enExample)
DE (1) DE112020004638T5 (enExample)
GB (1) GB2603345B (enExample)
WO (1) WO2021059052A1 (enExample)

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US11004819B2 (en) * 2019-09-27 2021-05-11 International Business Machines Corporation Prevention of bridging between solder joints
US11715755B2 (en) * 2020-06-15 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for forming integrated high density MIM capacitor
US11817392B2 (en) 2020-09-28 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit
US11574817B2 (en) * 2021-05-05 2023-02-07 International Business Machines Corporation Fabricating an interconnection using a sacrificial layer
US11735529B2 (en) * 2021-05-21 2023-08-22 International Business Machines Corporation Side pad anchored by next adjacent via
US20230114404A1 (en) * 2021-09-30 2023-04-13 Qualcomm Incorporated Embedded trace substrate (ets) with embedded metal traces having multiple thickness for integrated circuit (ic) package height control
JPWO2024202681A1 (enExample) * 2023-03-30 2024-10-03
TWI880644B (zh) * 2024-02-26 2025-04-11 創意電子股份有限公司 中介層裝置及半導體封裝裝置

Citations (6)

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US20170236724A1 (en) * 2014-09-30 2017-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for making multi-die package with bridge layer
US20180182707A1 (en) * 2016-12-22 2018-06-28 Intel Corporation Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same
US20180197846A1 (en) * 2013-03-15 2018-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Mechanisms for Dies With Different Sizes of Connectors
US10163798B1 (en) * 2017-12-22 2018-12-25 Intel Corporation Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same
US20190051605A1 (en) * 2017-08-10 2019-02-14 International Business Machines Corporation High-density interconnecting adhesive tape
US10361170B2 (en) * 2016-12-16 2019-07-23 Samsung Electronics Co., Ltd. Semiconductor package

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Publication number Priority date Publication date Assignee Title
US20180197846A1 (en) * 2013-03-15 2018-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Mechanisms for Dies With Different Sizes of Connectors
US20170236724A1 (en) * 2014-09-30 2017-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for making multi-die package with bridge layer
US10361170B2 (en) * 2016-12-16 2019-07-23 Samsung Electronics Co., Ltd. Semiconductor package
US20180182707A1 (en) * 2016-12-22 2018-06-28 Intel Corporation Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same
US20190051605A1 (en) * 2017-08-10 2019-02-14 International Business Machines Corporation High-density interconnecting adhesive tape
US10163798B1 (en) * 2017-12-22 2018-12-25 Intel Corporation Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same

Also Published As

Publication number Publication date
WO2021059052A1 (en) 2021-04-01
GB2603345A (en) 2022-08-03
US20210098349A1 (en) 2021-04-01
US11264314B2 (en) 2022-03-01
JP7617906B2 (ja) 2025-01-20
CN114342072B (zh) 2025-07-22
DE112020004638T5 (de) 2022-06-09
GB202204022D0 (en) 2022-05-04
JP2022550707A (ja) 2022-12-05
CN114342072A (zh) 2022-04-12

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