GB2406720B - An inductor formed in an integrated circuit - Google Patents

An inductor formed in an integrated circuit

Info

Publication number
GB2406720B
GB2406720B GB0421662A GB0421662A GB2406720B GB 2406720 B GB2406720 B GB 2406720B GB 0421662 A GB0421662 A GB 0421662A GB 0421662 A GB0421662 A GB 0421662A GB 2406720 B GB2406720 B GB 2406720B
Authority
GB
United Kingdom
Prior art keywords
conductive
inductor
aluminum
line
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0421662A
Other languages
English (en)
Other versions
GB2406720A (en
GB0421662D0 (en
Inventor
Edward Belden Harris
Sailesh Manish Merchant
Kurt George Steiner
Susan Clay Vitkavage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of GB0421662D0 publication Critical patent/GB0421662D0/en
Publication of GB2406720A publication Critical patent/GB2406720A/en
Application granted granted Critical
Publication of GB2406720B publication Critical patent/GB2406720B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/4902—Electromagnet, transformer or inductor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB0421662A 2003-09-30 2004-09-29 An inductor formed in an integrated circuit Expired - Fee Related GB2406720B (en)

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Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4948756B2 (ja) * 2003-09-30 2012-06-06 アギア システムズ インコーポレーテッド 集積回路内に形成されたインダクタ及びその製造方法
US7786836B2 (en) * 2005-07-19 2010-08-31 Lctank Llc Fabrication of inductors in transformer based tank circuitry
TWI304261B (en) 2005-10-12 2008-12-11 Realtek Semiconductor Corp Integrated inductor
US8669637B2 (en) * 2005-10-29 2014-03-11 Stats Chippac Ltd. Integrated passive device system
US7851257B2 (en) * 2005-10-29 2010-12-14 Stats Chippac Ltd. Integrated circuit stacking system with integrated passive components
US8409970B2 (en) 2005-10-29 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of making integrated passive devices
US8158510B2 (en) 2009-11-19 2012-04-17 Stats Chippac, Ltd. Semiconductor device and method of forming IPD on molded substrate
US8791006B2 (en) 2005-10-29 2014-07-29 Stats Chippac, Ltd. Semiconductor device and method of forming an inductor on polymer matrix composite substrate
US8188590B2 (en) * 2006-03-30 2012-05-29 Stats Chippac Ltd. Integrated circuit package system with post-passivation interconnection and integration
JP2008016502A (ja) * 2006-07-03 2008-01-24 Sharp Corp Ｒｆ集積回路及びその製造方法
US7791199B2 (en) * 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US8410578B2 (en) * 2006-12-29 2013-04-02 Semiconductor Components Industries, Llc Method of manufacturing a semiconductor component and structure
US7602027B2 (en) * 2006-12-29 2009-10-13 Semiconductor Components Industries, L.L.C. Semiconductor component and method of manufacture
JP5584474B2 (ja) * 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
US8212155B1 (en) * 2007-06-26 2012-07-03 Wright Peter V Integrated passive device
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
JP5578797B2 (ja) 2009-03-13 2014-08-27 ルネサスエレクトロニクス株式会社 半導体装置
US8395233B2 (en) * 2009-06-24 2013-03-12 Harris Corporation Inductor structures for integrated circuit devices
TWI389260B (zh) * 2009-09-30 2013-03-11 Inotera Memories Inc 半導體記憶體之電容下電極的製備方法
US8179221B2 (en) * 2010-05-20 2012-05-15 Harris Corporation High Q vertical ribbon inductor on semiconducting substrate
US8860390B2 (en) 2010-06-04 2014-10-14 Apple Inc. Switching power supply opposite polarity inductor arrangement
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8304855B2 (en) 2010-08-04 2012-11-06 Harris Corporation Vertical capacitors formed on semiconducting substrates
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8310328B2 (en) * 2010-10-07 2012-11-13 Touch Micro-System Technology Corp. Planar coil and method of making the same
KR101059490B1 (ko) * 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
KR101218985B1 (ko) * 2011-05-31 2013-01-04 삼성전기주식회사 칩형 코일 부품
US9159711B2 (en) * 2011-07-29 2015-10-13 GlobalFoundries, Inc. Integrated circuit systems including vertical inductors
US20130146345A1 (en) * 2011-12-12 2013-06-13 Kazuki KAJIHARA Printed wiring board and method for manufacturing the same
US9001031B2 (en) 2012-07-30 2015-04-07 Qualcomm Mems Technologies, Inc. Complex passive design with special via implementation
US8859419B2 (en) 2013-02-01 2014-10-14 Globalfoundries Inc. Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
US9263405B2 (en) * 2013-12-05 2016-02-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device
US10032850B2 (en) * 2016-05-11 2018-07-24 Texas Instruments Incorporated Semiconductor die with back-side integrated inductive component
US10263064B2 (en) * 2017-06-30 2019-04-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of forming the same
US11495555B2 (en) * 2018-03-14 2022-11-08 Intel Corporation Magnetic bilayer structure for a cored or coreless semiconductor package
US11270959B2 (en) * 2018-03-23 2022-03-08 Intel Corporation Enabling magnetic films in inductors integrated into semiconductor packages
US11355459B2 (en) * 2018-05-17 2022-06-07 Intel Corpoation Embedding magnetic material, in a cored or coreless semiconductor package
US10748810B2 (en) 2018-05-29 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing an integrated inductor with protections caps on conductive lines
US10756161B2 (en) * 2018-06-27 2020-08-25 Intel Corporation Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same
US11049820B2 (en) * 2018-07-30 2021-06-29 Texas Instruments Incorporated Crack suppression structure for HV isolation component
CN113364337A (zh) * 2021-06-24 2021-09-07 洛阳理工学院 一种柔性单电极摩擦纳米发电机
CN114360842B (zh) * 2021-12-28 2022-11-22 中国人民解放军海军工程大学 一种应用于高功率微波源的轻型化周期性磁场线圈

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446311A (en) * 1994-09-16 1995-08-29 International Business Machines Corporation High-Q inductors in silicon technology without expensive metalization
US6083802A (en) * 1998-12-31 2000-07-04 Winbond Electronics Corporation Method for forming an inductor
US6329234B1 (en) * 2000-07-24 2001-12-11 Taiwan Semiconductor Manufactuirng Company Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow
US6472285B1 (en) * 1999-04-30 2002-10-29 Winbond Electronics Corporation Method for fabricating high-Q inductance device in monolithic technology
US6573148B1 (en) * 2000-07-12 2003-06-03 Koninklljke Philips Electronics N.V. Methods for making semiconductor inductor
US20030157805A1 (en) * 2002-02-15 2003-08-21 Schultz Richard T. Thick traces from multiple damascene layers

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610433A (en) 1995-03-13 1997-03-11 National Semiconductor Corporation Multi-turn, multi-level IC inductor with crossovers
JPH09162357A (ja) * 1995-12-08 1997-06-20 Hitachi Ltd 高周波半導体装置
JP2904086B2 (ja) * 1995-12-27 1999-06-14 日本電気株式会社 半導体装置およびその製造方法
US5793272A (en) 1996-08-23 1998-08-11 International Business Machines Corporation Integrated circuit toroidal inductor
FR2771843B1 (fr) 1997-11-28 2000-02-11 Sgs Thomson Microelectronics Transformateur en circuit integre
KR100279753B1 (ko) * 1997-12-03 2001-03-02 정선종 반도체 집적회로 제조공정을 이용한 인덕터 제조방법
US6008102A (en) 1998-04-09 1999-12-28 Motorola, Inc. Method of forming a three-dimensional integrated inductor
JP3578644B2 (ja) * 1998-10-12 2004-10-20 Ｎｅｃエレクトロニクス株式会社 半導体装置
US6037649A (en) 1999-04-01 2000-03-14 Winbond Electronics Corp. Three-dimension inductor structure in integrated circuit technology
JP4005762B2 (ja) * 1999-06-30 2007-11-14 株式会社東芝 集積回路装置及びその製造方法
JP4200631B2 (ja) * 2000-03-29 2008-12-24 沖電気工業株式会社 オンチップ・コイルとその製造方法
US6429504B1 (en) 2000-05-16 2002-08-06 Tyco Electronics Corporation Multilayer spiral inductor and integrated circuits incorporating the same
US6847066B2 (en) * 2000-08-11 2005-01-25 Oki Electric Industry Co., Ltd. Semiconductor device
US6342424B1 (en) 2001-04-06 2002-01-29 National Semiconductor Corp. High-Q spiral inductor structure and methods of manufacturing the structure
US6650220B2 (en) * 2002-04-23 2003-11-18 Chartered Semiconductor Manufacturing Ltd. Parallel spiral stacked inductor on semiconductor material
US7135951B1 (en) * 2003-07-15 2006-11-14 Altera Corporation Integrated circuit inductors
JP4948756B2 (ja) * 2003-09-30 2012-06-06 アギア システムズ インコーポレーテッド 集積回路内に形成されたインダクタ及びその製造方法
US7167072B2 (en) * 2004-03-25 2007-01-23 United Microelectronics Corp. Method of fabricating inductor and structure formed therefrom

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446311A (en) * 1994-09-16 1995-08-29 International Business Machines Corporation High-Q inductors in silicon technology without expensive metalization
US6083802A (en) * 1998-12-31 2000-07-04 Winbond Electronics Corporation Method for forming an inductor
US6472285B1 (en) * 1999-04-30 2002-10-29 Winbond Electronics Corporation Method for fabricating high-Q inductance device in monolithic technology
US6573148B1 (en) * 2000-07-12 2003-06-03 Koninklljke Philips Electronics N.V. Methods for making semiconductor inductor
US6329234B1 (en) * 2000-07-24 2001-12-11 Taiwan Semiconductor Manufactuirng Company Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow
US20030157805A1 (en) * 2002-02-15 2003-08-21 Schultz Richard T. Thick traces from multiple damascene layers

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US20060192647A1 (en) 2006-08-31
JP4948756B2 (ja) 2012-06-06
US7068139B2 (en) 2006-06-27
US7541238B2 (en) 2009-06-02
GB0421662D0 (en) 2004-10-27
KR101045195B1 (ko) 2011-06-30
KR20050032009A (ko) 2005-04-06
TW200520195A (en) 2005-06-16
US7678639B2 (en) 2010-03-16
TWI362098B (en) 2012-04-11
US20050099259A1 (en) 2005-05-12
JP2005175434A (ja) 2005-06-30
US20090100668A1 (en) 2009-04-23

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