GB2291293A - Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop - Google Patents

Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Info

Publication number
GB2291293A
GB2291293A GB9518445A GB9518445A GB2291293A GB 2291293 A GB2291293 A GB 2291293A GB 9518445 A GB9518445 A GB 9518445A GB 9518445 A GB9518445 A GB 9518445A GB 2291293 A GB2291293 A GB 2291293A
Authority
GB
United Kingdom
Prior art keywords
phase
locked loop
clock signal
synchronizing signal
locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9518445A
Other versions
GB9518445D0 (en
GB2291293B (en
Inventor
Esa Laaksonen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of GB9518445D0 publication Critical patent/GB9518445D0/en
Publication of GB2291293A publication Critical patent/GB2291293A/en
Application granted granted Critical
Publication of GB2291293B publication Critical patent/GB2291293B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention relates to a method of generating a clock signal (CLK) by means of a phase-locked loop, and to a phase-locked loop comprising a phase comparator (10), a loop filter (102), and a voltage voltage-controlled oscillator (105). In the method, a synchronizing signal (MCLK) derived from a synchronisation source is applied to a first input in the phase comparator (101), and the clock signal is locked to the synchronizing signal. In order that the clock frequency could be kept unchanged even in failure situations, a control voltage sequence of oscillator (105) is stored in a memory (111) over a predetermined period of time while the clock signal is locked to the synchronizing signal, and a sequence obtained from the memory is substituted for the control voltage obtained from the phase comparator (101) in response to a change where a currently applied synchronizing signal becomes inadequate for use in timing. <IMAGE>
GB9518445A 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop Expired - Fee Related GB2291293B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI931020A FI93285C (en) 1993-03-08 1993-03-08 Method for generating a clock signal by means of a phase-locked loop and a phase-locked loop
PCT/FI1994/000077 WO1994021048A1 (en) 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Publications (3)

Publication Number Publication Date
GB9518445D0 GB9518445D0 (en) 1995-11-08
GB2291293A true GB2291293A (en) 1996-01-17
GB2291293B GB2291293B (en) 1997-03-05

Family

ID=8537511

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9518445A Expired - Fee Related GB2291293B (en) 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Country Status (5)

Country Link
AU (1) AU6143194A (en)
DE (1) DE4491211T1 (en)
FI (1) FI93285C (en)
GB (1) GB2291293B (en)
WO (1) WO1994021048A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2311178A (en) * 1996-03-14 1997-09-17 Nec Corp PLL synthesizers

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1281209B1 (en) * 1995-02-24 1998-02-17 Carpigiani Srl SOFT ICE CREAM MACHINE
EP0954104A1 (en) * 1998-04-28 1999-11-03 Siemens Aktiengesellschaft Phase locked loop comprising an analog phase comparator and a digital filter
DE10005152A1 (en) * 2000-02-07 2001-08-09 Deutsche Telekom Mobil Method for regenerating a clock signal from an HDB3-coded input signal and clock regenerator for performing the method
DE10150536B4 (en) 2001-10-12 2010-04-29 Infineon Technologies Ag Device for reconstructing data from a received data signal and corresponding transmitting and receiving device
DE60208964T2 (en) * 2002-11-21 2006-10-26 Sony Ericsson Mobile Communications Ab Oscillator frequency control
AU2003288128A1 (en) 2002-11-21 2004-06-15 Sony Ericsson Mobile Communications Ab Oscillator frequency control

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0347737A2 (en) * 1988-06-21 1989-12-27 Siemens Aktiengesellschaft Synchronisation method for a clock generator, especially of a clock generator of a digital telephone exchange
US5028885A (en) * 1990-08-30 1991-07-02 Motorola, Inc. Phase-locked loop signal generation system with control maintenance
EP0535397A2 (en) * 1991-09-30 1993-04-07 Siemens Aktiengesellschaft Circuit arrangement for synchronising a voltage-controlled oscillator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0347737A2 (en) * 1988-06-21 1989-12-27 Siemens Aktiengesellschaft Synchronisation method for a clock generator, especially of a clock generator of a digital telephone exchange
US5028885A (en) * 1990-08-30 1991-07-02 Motorola, Inc. Phase-locked loop signal generation system with control maintenance
EP0535397A2 (en) * 1991-09-30 1993-04-07 Siemens Aktiengesellschaft Circuit arrangement for synchronising a voltage-controlled oscillator

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
, E-948, abstract of JP, A, 2-100518 (NEC CORP), 12 April 1990 (12.04.90) *
CORP), 28 October 1987 (28.10.87) Patent abstracts of Japan, Vol 14,no.312 *
Patent abstracts of Japan, vol 12, no.118, E-600, abstract of JP, A, 62-247624 (MITSUBISHI ELECTRIC *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2311178A (en) * 1996-03-14 1997-09-17 Nec Corp PLL synthesizers
GB2311178B (en) * 1996-03-14 1998-05-27 Nec Corp Phase-locked loop circuit

Also Published As

Publication number Publication date
FI93285B (en) 1994-11-30
FI931020A (en) 1994-09-09
GB9518445D0 (en) 1995-11-08
AU6143194A (en) 1994-09-26
GB2291293B (en) 1997-03-05
DE4491211T1 (en) 1996-02-22
FI931020A0 (en) 1993-03-08
FI93285C (en) 1995-03-10
WO1994021048A1 (en) 1994-09-15

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20050303