AU6143194A - Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop - Google Patents

Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Info

Publication number
AU6143194A
AU6143194A AU61431/94A AU6143194A AU6143194A AU 6143194 A AU6143194 A AU 6143194A AU 61431/94 A AU61431/94 A AU 61431/94A AU 6143194 A AU6143194 A AU 6143194A AU 6143194 A AU6143194 A AU 6143194A
Authority
AU
Australia
Prior art keywords
phase
locked loop
generating
clock signal
locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU61431/94A
Inventor
Esa Laaksonen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of AU6143194A publication Critical patent/AU6143194A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal
AU61431/94A 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop Abandoned AU6143194A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FI931020A FI93285C (en) 1993-03-08 1993-03-08 Method for generating a clock signal by means of a phase-locked loop and a phase-locked loop
FI931020 1993-03-08
PCT/FI1994/000077 WO1994021048A1 (en) 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Publications (1)

Publication Number Publication Date
AU6143194A true AU6143194A (en) 1994-09-26

Family

ID=8537511

Family Applications (1)

Application Number Title Priority Date Filing Date
AU61431/94A Abandoned AU6143194A (en) 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Country Status (5)

Country Link
AU (1) AU6143194A (en)
DE (1) DE4491211T1 (en)
FI (1) FI93285C (en)
GB (1) GB2291293B (en)
WO (1) WO1994021048A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1281209B1 (en) * 1995-02-24 1998-02-17 Carpigiani Srl SOFT ICE CREAM MACHINE
JPH09246965A (en) * 1996-03-14 1997-09-19 Nec Corp Pll frequency synthesizer
EP0954104A1 (en) * 1998-04-28 1999-11-03 Siemens Aktiengesellschaft Phase locked loop comprising an analog phase comparator and a digital filter
DE10005152A1 (en) * 2000-02-07 2001-08-09 Deutsche Telekom Mobil Method for regenerating a clock signal from an HDB3-coded input signal and clock regenerator for performing the method
DE10150536B4 (en) 2001-10-12 2010-04-29 Infineon Technologies Ag Device for reconstructing data from a received data signal and corresponding transmitting and receiving device
ATE317180T1 (en) * 2002-11-21 2006-02-15 OSCILLATOR FREQUENCY CONTROL
JP4624796B2 (en) 2002-11-21 2011-02-02 ソニー エリクソン モバイル コミュニケーションズ， エービー Control of oscillation frequency

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980899A (en) * 1988-06-21 1990-12-25 Siemens Ag Method and apparatus for synchronization of a clock signal generator particularly useful in a digital telecommunications exchange
US5028885A (en) * 1990-08-30 1991-07-02 Motorola, Inc. Phase-locked loop signal generation system with control maintenance
DE9112177U1 (en) * 1991-09-30 1991-12-12 Siemens AG, 8000 München Circuit arrangement for synchronizing a voltage-controlled oscillator

Also Published As

Publication number Publication date
FI931020A0 (en) 1993-03-08
GB2291293B (en) 1997-03-05
FI93285C (en) 1995-03-10
GB2291293A (en) 1996-01-17
FI93285B (en) 1994-11-30
DE4491211T1 (en) 1996-02-22
WO1994021048A1 (en) 1994-09-15
FI931020A (en) 1994-09-09
GB9518445D0 (en) 1995-11-08

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