FI93285C - Method for generating a clock signal by means of a phase-locked loop and a phase-locked loop - Google Patents

Description

93285

The invention relates to a method according to the preamble of appended claim 1 for generating a clock signal by means of a phase-locked loop and to a phase-locked loop according to the preamble of appended claim 7. The primary field of application of the method according to the invention and the phase-locked loop 10 is slave oscillators of digital telecommunication systems, i.e. oscillators intended to lock into the master clock signal of the system.

In current digital transmission systems 15, synchronization can be performed either by means of separate synchronization connections or by utilizing normal data connections between the nodes (devices) of the system. Separate synchronization connections are used only in isolated cases and very rarely in the synchronization of the entire network. When using data connections for synchronization, the line code must be such that the nodes can also distinguish the clock frequency from the incoming data signal. Of these clock frequencies, synchronization of network nodes can be achieved by two different basic methods: mutual synchronization and slave synchronization.

In mutual synchronization, each node generates its own clock frequency from the average of the frequencies of the incoming signals and its own current clock frequency. Thus, all nodes in the network drift towards a common average frequency 30 and in steady state have reached it. However, a network using mutual synchronization cannot be made to synchronize to the desired source, in which case, for example, the interconnection of different networks is problematic, because then it is not possible to precisely determine the operating frequency of the entire network 35 in advance. In submissive synchronization, all nodes in the 2 93285 network are synchronized instead by one node, the so-called main node, clock frequency. Each node selects the frequency of one incoming signal as its own clock frequency source. The node tries to select a signal that has the clock frequency of the main node of the network.

In independent submissive synchronization, each node makes its own decision to synchronize without receiving any decision-supporting information from the outside. When nodes make their decision to synchronize independently, each node has to determine to which node it will synchronize. These determinations are often made in the form of a priority list, in which case the node selects the one with the highest priority from among the valid incoming signals as its synchronization source. If this signal is interrupted or degraded so that it can no longer be qualified as a synchronization source, the node selects the signal with the next highest priority from the list. The priority list must be selected so that all nodes on it are between that node and the master node, so that synchronization spreads to levels lower than the master node.

However, submissive stand-alone synchronization imposes limitations on synchronization: in a loop network, not all connections can be used for synchronization, so that the dynamic adaptability of the network 25 in different situations is limited. Communication must be established between the nodes so that the amount of information a single node has in all situations is sufficient for decision making without having to severely limit the number of connections used for synchronization, so that in the event of a fault the master node's clock frequency cannot be distributed to network nodes.

The simplest method of extending independent submissive synchronization to communicate is the so-called LP synchronization (loop protected). LP synchronization seeks to prevent timing interference in loop networks by using the above

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3 93285 is assisted by two status bits mcb and lcb, which are transmitted between the nodes of the network. The first status bit mcb (master control bit) indicates whether the network synchronization originates from the network node. The master node defined for network 5 transmits this bit as a logical zero in its outgoing signals, and the other nodes forward it if they are synchronized to a signal where the value of the mcb bit is zero. The second status bit lcb (loop control bit) indicates whether there is a loop in synchronization. Each node in the network 10 sends this bit as a logical one in the direction in which it is itself synchronized and as a logical zero in the other directions.

Each node uses its own priority list when selecting its synchronization source, but checks the mcb and lcb bits in addition to the sig-15 signal status before making a selection. The node primarily tries to find a connection whose clock frequency originates from the main node of the network (mcb = 0). If no such connection is found (due to a fault condition), the node selects the 20 highest working connections in the usual way. However, the selected connection (timing source) is always required to have its timing not in the loop (lcb = 0), even if the signal itself is otherwise valid for synchronization.

In order to avoid the heavy configurations of LP synchronization (which still usually have to be changed when adding or removing nodes from the network), the communication between the nodes must be extended from two state bits to messages. In such message-based submissive synchronization, the node is able to decide on its own synchronization by means of synchronization messages contained in the incoming signals. This eliminates the need for a priority list and allows all network connections to be used for synchronization. The synchronization message contains all the information that the node needs to synchronize. The node must know where the synchronization of the signal 4 93285 containing the synchronization message originates in order to synchronize to the clock frequency from the main node of the network. The messages must also contain enough other information so that the node can choose the best of the available options and 5 so that there are no loops for synchronization. One known message-based synchronization method is the so-called SOMS method (Self-Organizing Master-Slave synchronization), which is described in more detail in e.g. Finnish patent applications 925070-925074. Message-based synchronization methods 10 are further described, e.g., in U.S. Patents 2,986,723 and 4,837,850.

The method and phase-locked loop according to the present invention are intended for use in telecommunication networks using synchronization methods such as those described above, in which a node of the network has to synchronize with a master signal.

The problem with these networks is that when changes are made to the synchronization source, there are differences between the clock frequencies of the different devices (nodes) in the network. Such changes may be, for example, a failure of the master clock source or disconnection of some parts of the network. When parts of the network operate at different clock frequencies, bit error bursts occur between these parts. The greater the difference in clock frequencies, the greater the number of bursts.

Traditionally, oscillators in digital transmission systems have been controlled for free oscillation in the absence of an incoming master clock. Efforts have been made to adjust the free oscillation to the nominal center frequency during the manufacturing phase.

30 However, this method does not generally give good results, as • - the characteristics of the oscillator may have changed over time,

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5 93285 - the master clock frequency may differ from the nominal frequency, - when the oscillator changes from a free oscillation state to a locked state, or vice versa, strong momentary changes in frequency 5 may occur, and - the effect of temperature and other environmental factors cannot be taken into account, and

10 Improvements have also been made to the phase-locked loops to eliminate the above-mentioned shortcomings. Such an improvement is, for example, the reading of the voltage controlling the oscillator during normal operation via the A / D converter. In this case, when the interlock source is lost, the control voltage at the time of the interruption is applied from the memory to the D / A converter. The disadvantages of this method are: - the output voltage of the D / A converter cannot be adjusted steplessly, - the effect of temperature and other environmental factors cannot be taken into account, and - the vibration in the master clock cannot be taken into account.

It is therefore an object of the present invention to overcome the drawbacks described above and to provide a method by which the differences in clock frequencies used in different parts of a digital transmission network can be kept as small as possible during the time when synchronization between network parts is lost. This is achieved by the method according to the invention and the phase-locked loop 30a, the method being characterized by what is described in the characterizing part of the appended claim 1 and the phase-locked loop in turn by what is described in the characterizing part of the appended claim 7.

Thanks to the solution according to the invention, it is possible to keep the clock frequency 35 the same in the event of a network synchronization failure.

The invention will now be described in more detail by way of example with reference to Figure 1 of the accompanying drawing, which shows in block diagram form the structure of a phase-locked loop used in the method 5 according to the invention.

The phase-locked loop shown in Fig. 1 comprises, as is known per se, a phase comparator 101, a low-pass type loop filter 102 to which the output of the phase comparator is connected, and a voltage-controlled oscillator 105, the output of which is connected to the second reference input of the phase comparator. Connected to the second comparator input of the phase comparator is a master clock signal MCLK from a synchronization source (main network node) obtained from the node line-15 interface circuits 114. The phase comparator compares the phase of the signals at its inputs and generates a control signal proportional to the phase difference. This control signal is low-pass filtered by a loop filter 102 to a control signal Vc2. The clock signal CLK of the device (sol-20 mun) is obtained from the output of the voltage controlled oscillator 105, and as is well known, the phase locked loop tends to control the output signal of the oscillator so that there is no difference between the signals at the comparator inputs of the phase comparator, i.e. the oscillator output signal is locked to the frequency of the master clock signal.

According to the invention, a digital filter block 106 implemented by a processor is placed as part of a phase-locked loop, on the one hand by fitting an analog / digital converter 103 after the loop filter 102, the output signal of which is fed to the filter block and on the other frequency-controlling voltage-35 to Vc3.

7 93285

The filter or processor block 106 firstly comprises a digital low-pass filter 107, to the input of which the output signal of the analog-to-digital converter 103 is connected, and which performs additional filtering for the once low-pass filtered control voltage Vc2. In addition, the block comprises a monitoring unit 108 and a control unit 109 controlled by the monitoring unit and a selector 110 controlled by the control unit 109. In addition, a separate control voltage memory 111 is associated with the filter block, in which the control voltage variation sequence obtained from the filter 107 is stored for a certain length of time.

The output signal of the digital low-pass filter 107 is connected to the second input of the selector, and the output signal of the memory 111 is connected to the second input of the selector, either directly or via a separate calculation unit C. The selector output is connected to a digital-to-analog converter 104.

In practice, the entire filter block 106 can be implemented by some efficient communication processor, whereby the monitoring and control units can be implemented entirely in software. The processor can be, for example, type 68HC302 or some other general processor of equivalent level. Filter block 106, on the other hand, should not be implemented with a signal processor because the filtering load is light in typical use. (According to the current understanding, for example, a solution in which the bandwidth of the front filter 102 is about 100 Hz and the bandwidth is reduced to 10 Hz and no steepness higher than 20dB / decade is required. The processor power required for filtering would be increased by a front or lower steeple. )

The filter block is further associated with a real time clock 112 which provides time to the control unit 109 and which is backed up by a battery 113. The continuously updated memory 111 is preferably a non-volatile memory 35 which is backed up by the same battery. A real 8,93285 time clock is especially needed to store a long-term control voltage sequence (described below).

In addition, status or alarm information from the line interface circuits 114 of the device (node) is connected to the input of the monitoring unit 5 108.

It should also be noted that the divider typically present in the phase locked loop (between the oscillator and the phase comparator) is not shown in the figure because it is not relevant to the present invention.

The operation of the phase-locked loop according to the invention is as follows.

In the normal situation, where the clock signal CLK is locked to the master clock signal MCLK from the synchronization source (main network node), the control signal from the phase comparator 101 is filtered out of the low-pass mode.

It is passed through a loop filter 102 and a filtered control signal Vc2 is applied via an analog-to-digital converter 103 to a digital low-pass filter 107, from which it is further filtered and fed via a digital / analog converter 20 104 to a frequency control voltage Vc3. Thus, in this situation, the control unit 109 has directed the selector 110 to a position where the input to which the output signal of the digital low-pass filter 107 is connected is connected to the selector output. The detection of interlock 25 is based on status or alarm information from the interface circuits 114 to the monitoring unit, which may be, for example: - alarm information that a valid signal is present at the input from which the timing (master signal) is to be taken, - LP timing bits , it is not necessary to change the timing source, or - the status of the SOMS timing message is such that it is not necessary to change the timing source.

25 This normal mode stores digitally

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93285 9 the control voltage variation sequence from the low-pass filter 107 is continuously stored in memory under the control of the control unit 109. The length of the sequence in each memory depends on the intended use. If it can be assumed that the 5-network master oscillator is of good quality, especially in terms of long-term severity (temperature-compensated, etc.) and only needs to improve tolerance to short-term inaccuracies such as vibration errors, recording a few samples over a short period of time (eg a few 10 minutes) . If, on the other hand, it is desired to be able to compensate for frequency changes that occur over a longer period of time, such as changes caused by daily temperature fluctuations, the recording must be performed over the desired period. Typically, this will be one day. The sampling interval is limited mainly by the amount of memory allocated for the purpose, but in a reasonably constructed and functioning digital transmission network it is not possible to deviate at least more than ± 50 ppm from the center frequency unless timing errors occur and if the network remains "SDH synchronous" (e.g. ± 4.6 ppm), e.g., 512 samples (about 20 samples per hour) can be assumed to be sufficiently good.

When the monitoring unit 108 receives information from the interface circuits 114 of the device (node) that there is no longer a master clock signal valid as a locking source, the filter block 106 (processor) replaces the control voltage from the phase comparator with the sequence it takes from the memory. The detection of a need for compensation is based on status or alarm information received from line interface circuits 114, which may be, for example, the following information: - alarm information that a signal is missing from the input of the device (node) from which the timer (master clock signal) is taken, or alarm information, that the signal of the 35 inputs in question is weakened so that it can no longer be used for synchronization, - a change in the state of the LP timing bits so that it is necessary to change the timer source, or

If the samples have only been deposited over a short period of time, the most recent of these samples, which cannot be considered reliable due to system delays, shall be rejected. In other words, those samples which, at the time of the detection of the defect, can no longer be known with certainty from the master cell must be rejected. The remaining samples are averaged, and this average is coupled via selector 110 and D / A converter 104 to control oscillator 105. The calculation is illustrated in Figure 15 by its own unit C. If the samples are instead stored over a long period of time, the real-time clock 112 as well as the sequence of the correct starting point. This sequence is coupled (controlled by the control unit) via the selector 110 and the D / A converter 104 20 to control the oscillator 105. The shape of the control voltage generated by the sequence can be improved by calculating intermediate values between the stored samples in the calculation unit C.

The edge of the day-long sequence is well suited for 25, e.g. midnight. It is advantageous to keep in memory two sequences at a time, an available sequence and an editable sequence, which are exchanged at the edge of the sequence. (Information on which sequence is used must also be kept non-volatile.) 30 When a signal valid for timing is found again, the normal situation described above is returned to where the oscillator control voltage is obtained from the phase comparator.

Although the invention has been described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but may be modified within the scope of the inventive idea set forth above and in the appended claims. For example, the more detailed implementation of a filter block implemented by a processor to perform the same functions may vary. The solution according to the invention is also not necessarily tied to the generation of the clock signal of the node of the digital telecommunication network, but other similar applications are also possible.

Claims (10)

A method of generating a clock signal (CLK) by means of a phase-read loop, which loop comprises a phase comparator (101), a loop flicker (102) and a voltage controlled oscillator (105), and according to a method of synchronization source originating synchronization signal (MCLK), in which the clock signal is read, is fed to the first input of the phase comparator (101), characterized in that the control voltage sequence of the oscillator (105) is stored for a predetermined period of time in a memory (111). the clock signal is read in the synchronization signal, and the control voltage from the phase comparator (101) is replaced with the memory taken from the memory in response to a change where the currently used synchronization signal becomes inoperable for use in timing. 2. A method according to claim 1, characterized in that, on the basis of the voltage values of the sequence stored in the memory, an average is calculated, and the control voltage from the phase comparator is replaced by this average. Method according to claim 1, characterized in that the waveform of the sequence taken from the memory is improved by calculating intermediate values between the stored values. 4. A method according to claim 1, characterized in that the control voltage sequence is stored for a period of essentially one day. Method according to claim 4, characterized in that in the memory two sequences are poured into the thread, a sequence used to replace the control voltage and an editable sequence. Method according to claim 4, characterized in that 20 to 25 samples are taken per hour. A phase-read loop for generating a clock signal, which loop comprises a phase comparator (101), a loop filter (102) and a voltage controlled oscillator (105), wherein a synchronization signal originating from a synchronization source (MCLK) , in which the clock signal is read, is coupled to the input of the phase comparator (101), characterized in that it comprises means (107, 111, 112) for storing the control voltage sequence of the oscillator (105) for a predetermined period of time when the clock signal is read in the synchronization signal. and means (108 - 110, 112) for replacing the control signal from the phase comparator (101) with said sequence in response to a change where the currently used synchronization signal becomes inoperable for use in timing. A phase-read loop according to claim 7, characterized in that said storage means comprises a digital low-pass filter (107) and a non-volatile memory (111), in which sample from said low-pass filter is stored, and said replacement means comprises a selector (110). tili whose inputs signals from the digital low pass filter (107) and memory (111) are coupled. 9. Phase-read loop according to claim 7, characterized in that said storage and replacement means comprise a real-time clock (112) to provide the correct storage time and the right time for initiating the sequence. The phase-read loop according to claim 7, characterized in that it further comprises a calculation unit (C) for calculating intermediate values between the values stored in the memory (111).