GB2291548A - Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop - Google Patents

Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Info

Publication number
GB2291548A
GB2291548A GB9518446A GB9518446A GB2291548A GB 2291548 A GB2291548 A GB 2291548A GB 9518446 A GB9518446 A GB 9518446A GB 9518446 A GB9518446 A GB 9518446A GB 2291548 A GB2291548 A GB 2291548A
Authority
GB
United Kingdom
Prior art keywords
phase
loop
locked loop
synchronizing signal
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9518446A
Other versions
GB2291548B (en
GB9518446D0 (en
Inventor
Esa Laaksonen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of GB9518446D0 publication Critical patent/GB9518446D0/en
Publication of GB2291548A publication Critical patent/GB2291548A/en
Application granted granted Critical
Publication of GB2291548B publication Critical patent/GB2291548B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention relates to a method of generating a clock signal (CLK) by means of a phase-locked loop comprising a phase comparator (101), a loop filter (102), and a voltage-controlled oscillator (105), wherein a synchronizing signal (MCLK) derived from a synchronization source is applied to a first input in the phase comparator (101) and the clock signal is locked to the synchronizing signal, the locking of the loop being speeded up by increasing the bandwidth of the loop. In order that unnecessary changes in the clock frequency could be prevented and necessary changes could be speeded up, changes in a control voltage (Vc3) of the oscillator (105) are prevented temporarily in response to a change where a currently applied synchronizing signal becomes inadequate for use in timing, and the bandwidth of the loop is increased temporarily in response to a change where a synchronizing signal adequate for use in timing is again taken into use. <IMAGE>
GB9518446A 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop Expired - Fee Related GB2291548B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI931019A FI93286C (en) 1993-03-08 1993-03-08 Method of forming a clock signal with a phase-locked loop and phase-locked loop
PCT/FI1994/000076 WO1994021047A1 (en) 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Publications (3)

Publication Number Publication Date
GB9518446D0 GB9518446D0 (en) 1995-11-15
GB2291548A true GB2291548A (en) 1996-01-24
GB2291548B GB2291548B (en) 1997-01-08

Family

ID=8537510

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9518446A Expired - Fee Related GB2291548B (en) 1993-03-08 1994-03-03 Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Country Status (5)

Country Link
AU (1) AU6143094A (en)
DE (1) DE4491210T1 (en)
FI (1) FI93286C (en)
GB (1) GB2291548B (en)
WO (1) WO1994021047A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2317280A (en) * 1996-09-11 1998-03-18 Roke Manor Research Bandwidth adjustment in phase locked loops
GB2319409A (en) * 1996-11-15 1998-05-20 Nokia Telecommunications Oy Transceivers

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6345079B1 (en) * 1997-10-29 2002-02-05 Victor Company Of Japan, Ltd. Clock signal generation apparatus
FI20000638A (en) 2000-03-17 2001-09-18 Nokia Mobile Phones Ltd Adjustment of an oscillator

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0347737A2 (en) * 1988-06-21 1989-12-27 Siemens Aktiengesellschaft Synchronisation method for a clock generator, especially of a clock generator of a digital telephone exchange
EP0360442A1 (en) * 1988-09-02 1990-03-28 Nippon Telegraph and Telephone Corporation Frequency sythesizer
EP0376847A2 (en) * 1988-12-28 1990-07-04 Fujitsu Limited PLL synthesizer
US5028885A (en) * 1990-08-30 1991-07-02 Motorola, Inc. Phase-locked loop signal generation system with control maintenance

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0347737A2 (en) * 1988-06-21 1989-12-27 Siemens Aktiengesellschaft Synchronisation method for a clock generator, especially of a clock generator of a digital telephone exchange
EP0360442A1 (en) * 1988-09-02 1990-03-28 Nippon Telegraph and Telephone Corporation Frequency sythesizer
EP0376847A2 (en) * 1988-12-28 1990-07-04 Fujitsu Limited PLL synthesizer
US5028885A (en) * 1990-08-30 1991-07-02 Motorola, Inc. Phase-locked loop signal generation system with control maintenance

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CORP), 28, October 1987 (28.10.87) *
Patent abstracts of Japan, vol 12, no.118, E-600, abstract of JP, A, 62-247624 (MITSUBISHI ELECTRIC *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2317280A (en) * 1996-09-11 1998-03-18 Roke Manor Research Bandwidth adjustment in phase locked loops
GB2319409A (en) * 1996-11-15 1998-05-20 Nokia Telecommunications Oy Transceivers
GB2319409B (en) * 1996-11-15 1999-01-27 Nokia Telecommunications Oy Apparatus and method for stabilising the frequency of a phase locked loop

Also Published As

Publication number Publication date
FI93286B (en) 1994-11-30
GB2291548B (en) 1997-01-08
DE4491210T1 (en) 1996-02-22
FI931019A0 (en) 1993-03-08
GB9518446D0 (en) 1995-11-15
FI931019A (en) 1994-09-09
FI93286C (en) 1995-03-10
WO1994021047A1 (en) 1994-09-15
AU6143094A (en) 1994-09-26

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20110303