GB2319409A

GB2319409A - Transceivers

Info

Publication number: GB2319409A
Application number: GB9623872A
Authority: GB
Inventors: Mark Sherlock
Original assignee: Nokia Telecommunications Oy
Current assignee: Nokia Oyj
Priority date: 1996-11-15
Filing date: 1996-11-15
Publication date: 1998-05-20
Anticipated expiration: 2016-11-15
Also published as: WO1998023034A2; GB2319409B; GB9623872D0; AU5052898A; WO1998023034A3

Abstract

Traditional radio transceivers, such as those used in the base stations of cellular mobile systems require delicate manual tuning. Regardless of the accuracy of the initial tuning, an uncompensated oscillator provides little compensation for temperature drift and component ageing. The invention provides a method of stabilising the frequency of a phase locked loop provided that a stable reference voltage (VREF) is available. During recalibraton, control unit (7) applies, via switch (SW1), reference voltage (VREF) to the input of a voltage controlled oscillator (6). An adjustable control element (5) of the oscillator is adjusted until the frequency of the oscillator (6) is within a predetermined deviation from its nominal value. Detecting either a period without any up or down pulses originating from phase detector (2), or that the output voltage of integrator (4) equals the reference voltage (VREF) indicates correct tuning. The control unit (7) is enabled by a signal EN from a radio station and controls the switch SW1 and the gain of element (5) in dependence of a signal indicative of frequency difference between oscillator (6) and a reference signal frequencies.

Description

Apparatus and method for stabilising the frequency of a phase locked loop The invention relates to radio transceivers and more particularly to a method and a device for improving both the short-term and long-term stability of radio frequency oscillators.

In order to fulfil the requirements for high transmission capability of modem communication systems, the available bandwidths must be utilised to the fullest extent possible. The frequencies of radio transceivers, such as those used in the base stations of cellular mobile systems, are generated with phase locked loop (PLL) circuits. For tuning the output frequencies of such circuits to their nominal frequencies, delicate manual tuning has been required.

Regardless of the accuracy of the initial tuning, an uncompensated oscillator provides little compensation for temperature drift and component ageing.

It is the object of this invention to achieve an apparatus for and a method of providing RF oscillators with a good short-term and long-term stability without requiring the labour-intensive manual tuning phase. The object of the invention is achieved with the characteristic features of the attached claims.

The invention is based on a control circuit placed inside a phase locked loop, whereby the control circuit, upon detecting an enable signal from the operation and maintenance (O & M) section of the radio station, re-calibrates the phase locked loop by applying a correction signal to the input voltage of the voltage controlled oscillator within the PLL.

The invention will now be described in more detail with reference to the preferred embodiments, given only by way of example, and illustrated in the accompanying drawings, wherein: Fig. 1 shows a block diagram of a conventional phase locked loop; Fig. 2 shows a block diagram of the phase locked loop of Fig. 1 enhanced with the inventive stabilising circuit comprising a digital evaluation circuit; Fig. 3 shows as a block diagram the circuit of Fig. 2 wherein the stabilising circuit comprises an analogue evaluation circuit; Fig. 4 shows a component-level diagram of a control circuit for the phase locked loop of Fig. 3.

Fig. 1 shows a block diagram of a conventional phase locked loop. A phase detector 2 detects whether the outpu. frequency fvco of the voltage controlled oscillator (VCO) 6 is higher or lower than a reference frequency fREF. If fvco < fREF the phase detector 2 produces pulses at its Up output U. If fvco > the phase detector 2 produces pulses at its Down output D. The width of the pulses is proportional to the difference between the frequencies. If the frequencies are equal, no pulses will be produced.

If a reference frequency other than the desired output frequency is available, dividers 1 and/or 1' can optionally be installed at one or both of the inputs of the phase detector 2 to divide the frequencies fREF and/or fvco by positive integers R and/or N, respectively, before applying the frequencies to the inputs of the phase detector.

A charge pump 3 converts these Up and Down pulses into a bipolar output signal. Integrator 4 converts this bipolar signal into a DC voltage. As an example, the integrator consists of an operational amplifier having a capacitor in its feedback loop. Other types of active or passive integrators and filters can be used as well.

Without the feedback provided by the phase locked loop, the VCO 6 should, e.g. in a DCS system, have an output frequency of approximately 1800+3.5 MHz for transmitting or 1600+3.5 MHz for receiving when the input voltage Vt to the VCO 6 is a given DC value.

Fig. 2 shows as a block diagram the phase locked loop of Fig. 1 enhanced with a digital stabilising circuit of the present invention. A control circuit 7 has two sense inputs, namely the Up and Down signals U, D, from the phase detector 2. In addition, the control circuit 7 has an enable input EN, obtained from the O & M section of the radio station. Optionally, the control circuit 7 may also have a status output RDY reporting that the adjustmerit has been accomplished. However, since the calibration function always improves the accuracy of the phase locked loop, the control section of the radio station can simply use the enable signal EN to temporarily permit the operation of the control circuit 7 and restore normal operation at any time. The phase locked loop is ready for normal operation as soon as switch SW1 is restored to the normal position.

VREF is a conventional reference voltage. The stability of VREF determines the stability of the phase locked loop. The intended location of the inventive circuit is within radio stations comprising multiple transceivers. In such an environment, a single reference voltage can be utilised by all the transceivers within the radio station.

SW1 is any switch with a control line, preferably an analogue switch.

The adjustable control element 5 can be a separate gain or attenuation stage or it can be an adjustable component within the VCO 6. It is only for the purpose of illustration that the control element 5 is shown as a separate gain stage. The control element 5 must maintain its setting after the normal operation of the PLL has been restored. Appropriate adjustable elements include: (i) an electrically adjustable potentiometer, EPOT; (ii) an analogue sample and hold circuit in connection with a voltage-adjustable amplifier; (iii) same as (ii) but comprising a digital latch and a DAC, and (iv) a resistor matrix consisting of resistors and analogue switches.

Upon receiving an active enable signal EN, the control unit 7 operates in these steps: (i) connecting SW1 to position VREF; (ii) adjusting control element 5 to increase or decrease the frequency of the VCO, depending on whether an Up pulse U or a Down pulse D, respectively is received; (iii) after detecting either a period without an Up pulse U or a Down pulse D, or that the Enable signal is deactivated, restoring switch SW1 to normal position and optionally, outputting a status signal of ready (RDY).

The circuitry of Fig. 3 is a variation of that of Fig. 2. In the circuit of Fig.

3, the decisions in the control circuit 7 are based on the output of a comparator 8 comparing the output voltage of the integrator 4 to the reference voltage VREF.

If the comparator 8 is a simple on/off comparator the control circuit has no way of knowing whether the output frequency f,co is within specified limits. In this case, the control circuit can not output a ready signal RDY. Instead, it must keep adjusting, up or down, for as long as the enable signal is active.

If the comparator 8 is a window comparator with two outputs, the control circuit receives via one output OK the information whether or not the output frequency t,co is within specified limits. The other output UD of comparator 8 signals whether the output frequency fvco should be adjusted up or down. In this case, the control circuit 7 can output a ready signal RDY as soon as it senses an active signal from the output OK of the window comparator.

Fig. 4 shows a component-level diagram of an appropriate control unit. The circuit of Fig. 4 performs the functions of the blocks 5, 7 and 8 in Fig.

3. In Fig. 4, comparators Al, A2 and resistors R1-R3 form the window comparator shown as block 8 in Fig. 3. The output of Al is high if Vt is lower than the voltage at the junction R1-R2. For a moment, suppose that electrically adjustable potentiometer EPOT receives clock pulses at its increment input INC from oscillator N2, R4, C1. In this case, potentiometer EPOT steps upwards since its direction input, U/D (upidown), is obtained from the output of comparator Al. However, potentiometer EPOT steps downwards if V, is higher than the voltage at the junction of R1 and R2. The output of comparator A2 is high if V1 is higher than the voltage at the junction of R2 and R3. For the values of Vt inside the "window", or range of voltages between the voltages at the terminals of R2, the outputs of both comparators Al and A2 are high. In this case, the output of NAND gate N3 is low, preventing the pulses from the oscillator N2, R4, C1 from reaching the increment input INC of potentiometer EPOT. The output of N3 can also be used as a status signal RDY indicating that the voltage Vt and thus the frequency of the loop is within predetermined limits. The circuit of Fig. 4 is enabled with the enable signal EN which is active when at logic "0". This signal is used as a chip select for potentiometer EPOT and it also enables oscillator N2, R4, C1 after a small delay caused by N1, R5, C2. This delay prevents autotuning until the transients caused by changing modes have decayed. The output of the potentiometer EPOT can be used in many ways to control the frequency of the VCO. For example, the potentiometer EPOT can be connected as a voltage divider between a reference voltage and ground. In this case the voltage at the wiper of the potentiometer can be simply applied as input voltage to the VCO.

The control circuit according to the invention eliminates the costly manual tuning step of the phase locked loop. In addition, the inventive circuit compensates for the drifts due to temperature and component ageing.

While particular embodiments of the invention have been described, the invention is not limited thereto since many modifications can be made by persons skilled in the art without departing from the spirit and scope of the attached claims.

Claims

CLAIMS:

1. A phase locked loop comprising: voltage controlled oscillator means (6) having an input and an output wherein the frequency (fvco) at said output is responsive to an input voltage (VJ at said input; phase detector means (2) with a first input for receiving a reference signal (fREF) and a second input for receiving a signal from said output of said oscillator means (6), for generating output signals indicating whether the frequency at said first input is higher or lower than the frequency at said second input; filter means (4) operationally connected to said phase detector means (2) and converting the output signal of said phase detector means (2) into an essentially DC voltage, said DC voltage being operationally connected to the input of said voltage controlled oscillator means (6); characterized in that said phase locked loop also comprises: control means (7) having at least one input responsive to signals indicating whether said output frequency (fvco) of said oscillator means (6) is higher or lower than said reference signal (fret); and at least one output signal for controlling the input voltage (\/ to said oscillator means (6); adjustable control element (5), arranged to control the frequency of the oscillator means (6) and responsive to a control signal from said control means (7); means for receiving a reference voltage (ref); selector means (SW1) capable of selectively connecting, under the control of control means (7), the input of said oscillator means (6) to said reference voltage (VREF)

2. Phase locked loop of claim 1, characterized in that said phase detector means (2) comprises a first output (U) responsive to the frequency at said first input being higher than the frequency at said second input; and a second output (D) responsive to the frequency at said first input being lower than the frequency at said second input; and said control means (7) comprises a first input connected to said first output (U) of said phase detector means (2},and a second input connected to said second output (D) of said phase detector means (2);

3. Phase locked loop of claim 1, characterized in that said phase locked loop also comprises comparison means (8) having at least two inputs and at least one output, said comparison means (8) being arranged to compare said output DC voltage of said filter means (4) to said reference voltage (VREF) and said outputs of said comparison means (8) being operationally connected said inputs of said control means (7).

4. Phase locked loop of claim 1, characterized in that said adjustable control element (5) comprises an electrically adjustable potentiometer.

5. Phase locked loop of claim 1, characterized in that said adjustable control element (5) comprises a sample and hold circuit connected to a voltage controlled amplifier.

6. Phase locked loop of claim 1, characterized in that said adjustable control element (5) comprises a resistor matrix consisting of resistors and analogue switches.

7. Phase locked loop of claim 1, characterized in that said phase locked loop is installed in a base station of a cellular communications system and said control means (7) further comprises input means (EN) permitting the base station to enable the control means (7).

8. Phase locked loop of claim 7, characterized in that said control means (7) further comprises an output signal (RDY) indicating that the frequency of said oscillator means (6) is within a predetermined deviation from its nominal value.

9. Method of adjusting the frequency of a phase locked loop wherein said phase locked loop comprises: a voltage controlled oscillator (6) having an input and an output wherein the frequency (fvco) at said output is responsive to an input voltage (V,) at said input; a phase detector (2) with a first input for receiving a reference signal (fREF) and a second input for receiving a signal from said output of said oscillator (6), and with a plurality of outputs indicating whether the frequency at said first input is higher or lower than the frequency at said second input; a filter (4) operationally connected to the output of said phase detector (2) and converting the signal at said output into an essentially DC voltage, said DC voltage being operationally connected to the input of said voltage controlled oscillator (6); and means for receiving a reference voltage (VREF), characterized in that said method comprises the following steps: (i) connecting the input of said oscillator (6) to said reference voltage O/REF) ; (ii) adjusting an adjustable element (5) within said phase locked loop; (iii) reconnecting said input of said oscillator (6) to receive said output DC voltage of said filter means (4).

10. Method of claim 9, characterized in that said method of adjusting is initiated upon detecting an enable signal (EN) from the radio station.

11. Method of claim 10, characterized in that said method further comprises the step of producing a ready signal (RDY) indicating said output frequency (fvco) of said oscillator means (6) is within a predetermined deviation from its nominal value.

12. Method of claim 9, characterized in that said step of adjusting is terminated upon detecting a predetermined period of time where no output signals originate from said phase detector (2).

13. Method of claim 9, characterized in that said step of adjusting is terminated upon detecting a control signal from the radio station.

14. A phase locked loop substantially as hereinbefore described with reference to Figures 2 to 4 of the accompanying drawings.

1 5. A method of adjusting the frequency of a phase locked loop, substantially as hereinbefore described with reference to Figures 2 to 4 of the accompanying drawings.