WO1998023034A2 - Apparatus and method for stabilising the frequency of a phase locked loop - Google Patents

Apparatus and method for stabilising the frequency of a phase locked loop Download PDF

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Publication number
WO1998023034A2
WO1998023034A2 PCT/FI1997/000691 FI9700691W WO9823034A2 WO 1998023034 A2 WO1998023034 A2 WO 1998023034A2 FI 9700691 W FI9700691 W FI 9700691W WO 9823034 A2 WO9823034 A2 WO 9823034A2
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WO
WIPO (PCT)
Prior art keywords
input
output
frequency
locked loop
phase locked
Prior art date
Application number
PCT/FI1997/000691
Other languages
French (fr)
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WO1998023034A3 (en
Inventor
Mark Sherlock
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to AU50528/98A priority Critical patent/AU5052898A/en
Publication of WO1998023034A2 publication Critical patent/WO1998023034A2/en
Publication of WO1998023034A3 publication Critical patent/WO1998023034A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal

Definitions

  • the invention relates to radio transceivers and more particularly to a method and a device for improving both the short-term and long-term stability of radio frequency oscillators.
  • Fig. 1 shows a block diagram of a conventional phase locked loop
  • Fig. 2 shows a block diagram of the phase locked loop of Fig. 1 enhanced with the inventive stabilising circuit comprising a digital evaluation circuit;
  • Fig. 3 shows as a block diagram the circuit of Fig. 2 wherein the stabilising circuit comprises an analogue evaluation circuit
  • Fig. 4 shows a component-level diagram of a control circuit for the phase locked loop of Fig. 3.
  • Fig. 1 shows a block diagram of a conventional phase locked loop.
  • a phase detector 2 detects whether the output frequency f vc0 of the voltage controlled oscillator (VCO) 6 is higher or lower than a reference frequency f REF . If f co ⁇ . tne phase detector 2 produces pulses at its Up output U. If f vco > f REF the phase detector 2 produces pulses at its Down output D. Typically, the width of the pulses is proportional to the difference between the frequencies. If the frequencies are equal, no pulses will be produced.
  • VCO voltage controlled oscillator
  • dividers 1 and/or can optionally be installed at one or both of the inputs of the phase detector 2 to divide the frequencies f REF and/or f vco by positive integers R and/or N, respectively, before applying the frequencies to the inputs of the phase detector 2.
  • a charge pump 3 converts these Up and Down pulses into a bipolar output signal.
  • Integrator 4 converts this bipolar signal into a DC voltage.
  • the integrator consists of an operational amplifier OA having a capacitor C in its feedback loop.
  • Other types of active or passive integrators and filters can be used as well.
  • Fig. 2 shows as a block diagram the phase locked loop of Fig. 1 enhanced with a digital stabilising circuit of the present invention.
  • a control circuit 7 receives the output signal(s) of the phase detector 2.
  • the control circuit 7 has two sense inputs, namely the Up and Down signals U, D, from the phase detector 2.
  • the control circuit 7 also has an enable input EN, obtained from the O&M section of the radio station.
  • control circuit 7 may also have a status output RDY reporting that the adjustment has been accomplished.
  • the control section of the radio station can simply use the enable signal EN to permit temporarily the operation of the control circuit 7 and restore normal operation at any time.
  • the phase locked loop is ready for normal operation as soon as a switch SW 1 (described below) is restored to the normal position.
  • V REF is a conventional reference voltage.
  • the stability of V REF determines the stability of the phase locked loop.
  • the intended location of the inventive circuit is within radio stations comprising multiple transceivers. In such an environment, a single reference voltage can be utilised by all the transceivers within the radio station.
  • the switch SW. is any switch with a control line, preferably an analogue switch.
  • the adjustable control element 5 can be a separate gain or attenuation stage, or it can be an adjustable component within the VCO 6. It is only for the purpose of illustration that the control element 5 is shown as a separate gain stage. The control element 5 must maintain its setting after the normal operation of the PLL has been restored.
  • Appropriate adjustable elements include: (i) an electrically adjustable potentiometer, EPOT; (ii) an analogue sample and hold circuit in connection with a voltage-adjustable amplifier; (iii) same as (ii) but comprising a digital latch and a DAC, and (iv) a resistor matrix consisting of resistors and analogue switches.
  • control unit 7 Upon receiving an active enable signal EN, the control unit 7 operates by these steps:
  • the decisions in the control circuit 7 are based on the output of a comparator 8 comparing the output voltage of the integrator 4 with the reference voltage V REF . If the comparator 8 is a simple on/off comparator, the control circuit has no way of knowing whether the output frequency f vco is within the specified limits. In this case, the control circuit cannot output a ready signal RDY. Instead, it must keep adjusting, up or down, for as long as the enable signal is active.
  • the control circuit 7 receives via one output OK the information whether or not the output frequency f vco is within the specified limits.
  • the other output UD of comparator 8 signals whether the output frequency f vc0 should be adjusted up or down.
  • the control circuit 7 can output a ready signal RDY as soon as it senses an active signal from the output OK of the window comparator.
  • Fig. 4 shows a component-level diagram of an appropriate control unit.
  • the circuit of Fig. 4 performs the functions of blocks 5, 7 and 8 in Fig. 3.
  • comparators A1 , A2 and resistors R1-R3 form the window comparator shown as block 8 in Fig. 3.
  • the output of A1 is high if V, is lower than the voltage at the junction R1-R2.
  • an electrically adjustable potentiometer EPOT receives clock pulses at its increment input INC from an oscillator N2, R4, C1.
  • the potentiometer EPOT steps upwards since its direction input, U/D (up/down), is obtained from the output of the comparator A1.
  • the potentiometer EPOT steps downwards if V t is higher than the voltage at the junction of R1 and R2.
  • the output of the comparator A2 is high if V, is higher than the voltage at the junction of R2 and R3. For the values of V, inside the "window", or the range of voltages between the voltages at the terminals of R2, the outputs of both comparators A1 and A2 are high. In this case, the output of NAND gate N3 is low, preventing the pulses from the oscillator N2, R4, C1 from reaching the increment input INC of the potentiometer EPOT. The output of N3 can also be used as a status signal RDY indicating that the voltage V, and thus the frequency of the loop is within predetermined limits.
  • the circuit of Fig. 4 is enabled with the enable signal EN which is active when at logic "0".
  • This signal is used as a chip select for the potentiometer EPOT and it also enables oscillator N2, R4, C1 after a small delay caused by N1 , R5, C2. This delay prevents autotuning until the transients caused by changing between the normal mode and tuning have decayed.
  • the output of the potentiometer EPOT can be used in many ways to control the frequency of the VCO.
  • the potentiometer EPOT can be connected as a voltage divider between a reference voltage and ground. In this case the voltage at the wiper of the potentiometer can be simply applied as input voltage to the VCO.
  • control circuit eliminates the costly manual tuning step of a phase locked loop.
  • inventive circuit compensates for drifts due to temperature and component ageing.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Traditional radio transceivers, such as those used in the base stations of cellular mobile systems require delicate manual tuning. Regardless of the accuracy of the initial tuning, an uncompensated oscillator provides little compensation for temperature drift and component ageing. The invention provides a way of stabilising the frequency of a phase locked loop, provided that a stable reference voltage (VREF) is available. During recalibration, control unit (7) applies, via switch (SW1), reference voltage (VREF) to the input of a voltage controled oscillator (6). An adjustable control element (5) of the oscillator is adjusted until the frequency of the oscillator (6) is within a predetermined deviation from its nominal value. Correct tuning can be detected either by detecting a period without any up (U) or down (D) pulses originating from phase detector (2), or by detecting that the output voltage of integrator (4) equals the reference voltage (VREF).

Description

Apparatus and method for stabilising the frequency of a phase locked loop
The invention relates to radio transceivers and more particularly to a method and a device for improving both the short-term and long-term stability of radio frequency oscillators.
In order to fulfil the requirements for high transmission capability of modern communication systems, the available bandwidths must be utilised to the fullest extent possible. The frequencies of radio transceivers, such as those used in the base stations of cellular mobile systems, are generated with phase locked loop (PLL) circuits. For tuning the output frequencies of such circuits to their nominal frequencies, delicate manual tuning has been required. Regardless of the accuracy of the initial tuning, an uncompensated oscillator provides little compensation for temperature drift and component ageing.
It is an object of this invention to achieve an apparatus and a method for providing RF oscillators with a good short-term and long-term stability without requiring the labour-intensive manual tuning phase. The object of the invention is achieved with the characteristic features of the attached independent claims. The preferred embodiments of the invention are disclosed in the dependent claims. The invention is based on a control circuit placed inside a phase locked loop, whereby the control circuit, upon detecting an enable signal from the operation and maintenance (O&M) section of the radio station, re-calibrates the phase locked loop by applying a correction signal to the input voltage of the voltage controlled oscillator within the PLL. The invention will now be described in more detail with reference to the preferred embodiments, given only by way of example, and illustrated in the accompanying drawings, wherein:
Fig. 1 shows a block diagram of a conventional phase locked loop;
Fig. 2 shows a block diagram of the phase locked loop of Fig. 1 enhanced with the inventive stabilising circuit comprising a digital evaluation circuit;
Fig. 3 shows as a block diagram the circuit of Fig. 2 wherein the stabilising circuit comprises an analogue evaluation circuit; and
Fig. 4 shows a component-level diagram of a control circuit for the phase locked loop of Fig. 3.
Fig. 1 shows a block diagram of a conventional phase locked loop. A phase detector 2 detects whether the output frequency fvc0 of the voltage controlled oscillator (VCO) 6 is higher or lower than a reference frequency fREF. If f co < . tne phase detector 2 produces pulses at its Up output U. If fvco > fREF the phase detector 2 produces pulses at its Down output D. Typically, the width of the pulses is proportional to the difference between the frequencies. If the frequencies are equal, no pulses will be produced.
If a reference frequency other than the desired output frequency is available, dividers 1 and/or can optionally be installed at one or both of the inputs of the phase detector 2 to divide the frequencies fREF and/or fvco by positive integers R and/or N, respectively, before applying the frequencies to the inputs of the phase detector 2.
A charge pump 3 converts these Up and Down pulses into a bipolar output signal. Integrator 4 converts this bipolar signal into a DC voltage. As an example, the integrator consists of an operational amplifier OA having a capacitor C in its feedback loop. Other types of active or passive integrators and filters can be used as well.
Without the feedback provided by the phase locked loop, the VCO 6 should, e.g. in a DCS system (also known as GSM 1800), have an output frequency of approximately 1800+3.5 MHz for transmitting or 1600+3.5 MHz for receiving when the input voltage V, to the VCO 6 is a given DC value. Fig. 2 shows as a block diagram the phase locked loop of Fig. 1 enhanced with a digital stabilising circuit of the present invention. A control circuit 7 receives the output signal(s) of the phase detector 2. In this case, the control circuit 7 has two sense inputs, namely the Up and Down signals U, D, from the phase detector 2. Preferably, the control circuit 7 also has an enable input EN, obtained from the O&M section of the radio station. Optionally, the control circuit 7 may also have a status output RDY reporting that the adjustment has been accomplished. However, since the calibration function always improves the accuracy of the phase locked loop, the control section of the radio station can simply use the enable signal EN to permit temporarily the operation of the control circuit 7 and restore normal operation at any time. The phase locked loop is ready for normal operation as soon as a switch SW1 (described below) is restored to the normal position.
VREF is a conventional reference voltage. The stability of VREF determines the stability of the phase locked loop. The intended location of the inventive circuit is within radio stations comprising multiple transceivers. In such an environment, a single reference voltage can be utilised by all the transceivers within the radio station. The switch SW., is any switch with a control line, preferably an analogue switch. The adjustable control element 5 can be a separate gain or attenuation stage, or it can be an adjustable component within the VCO 6. It is only for the purpose of illustration that the control element 5 is shown as a separate gain stage. The control element 5 must maintain its setting after the normal operation of the PLL has been restored. Appropriate adjustable elements include: (i) an electrically adjustable potentiometer, EPOT; (ii) an analogue sample and hold circuit in connection with a voltage-adjustable amplifier; (iii) same as (ii) but comprising a digital latch and a DAC, and (iv) a resistor matrix consisting of resistors and analogue switches.
Upon receiving an active enable signal EN, the control unit 7 operates by these steps:
(i) connecting the SW1 to position VREF;
(ii) adjusting the control element 5 to increase or decrease the frequency of the VCO, depending on whether an Up pulse U or a Down pulse D, respectively, is received;
(iii) after detecting either a period without an Up pulse U or a Down pulse D, or that the enable signal EN is deactivated, restoring the switch SW1 to the normal position and optionally, outputting a status signal of ready (RDY). The circuit of Fig. 3 is a variation of that of Fig. 2. In the circuit of Fig.
3, the decisions in the control circuit 7 are based on the output of a comparator 8 comparing the output voltage of the integrator 4 with the reference voltage VREF. If the comparator 8 is a simple on/off comparator, the control circuit has no way of knowing whether the output frequency fvco is within the specified limits. In this case, the control circuit cannot output a ready signal RDY. Instead, it must keep adjusting, up or down, for as long as the enable signal is active.
If the comparator 8 is a window comparator with two outputs, the control circuit 7 receives via one output OK the information whether or not the output frequency fvco is within the specified limits. The other output UD of comparator 8 signals whether the output frequency fvc0 should be adjusted up or down. In this case, the control circuit 7 can output a ready signal RDY as soon as it senses an active signal from the output OK of the window comparator.
Fig. 4 shows a component-level diagram of an appropriate control unit. The circuit of Fig. 4 performs the functions of blocks 5, 7 and 8 in Fig. 3. In
Fig. 4, comparators A1 , A2 and resistors R1-R3 form the window comparator shown as block 8 in Fig. 3. The output of A1 is high if V, is lower than the voltage at the junction R1-R2. For a moment, suppose that an electrically adjustable potentiometer EPOT receives clock pulses at its increment input INC from an oscillator N2, R4, C1. In this case, the potentiometer EPOT steps upwards since its direction input, U/D (up/down), is obtained from the output of the comparator A1. However, the potentiometer EPOT steps downwards if Vt is higher than the voltage at the junction of R1 and R2. The output of the comparator A2 is high if V, is higher than the voltage at the junction of R2 and R3. For the values of V, inside the "window", or the range of voltages between the voltages at the terminals of R2, the outputs of both comparators A1 and A2 are high. In this case, the output of NAND gate N3 is low, preventing the pulses from the oscillator N2, R4, C1 from reaching the increment input INC of the potentiometer EPOT. The output of N3 can also be used as a status signal RDY indicating that the voltage V, and thus the frequency of the loop is within predetermined limits. The circuit of Fig. 4 is enabled with the enable signal EN which is active when at logic "0". This signal is used as a chip select for the potentiometer EPOT and it also enables oscillator N2, R4, C1 after a small delay caused by N1 , R5, C2. This delay prevents autotuning until the transients caused by changing between the normal mode and tuning have decayed. The output of the potentiometer EPOT can be used in many ways to control the frequency of the VCO. For example, the potentiometer EPOT can be connected as a voltage divider between a reference voltage and ground. In this case the voltage at the wiper of the potentiometer can be simply applied as input voltage to the VCO.
The control circuit according to the invention eliminates the costly manual tuning step of a phase locked loop. In addition, the inventive circuit compensates for drifts due to temperature and component ageing.
While particular embodiments of the invention have been described, the invention is not limited thereto, since many modifications can be made by persons skilled in the art without departing from the scope of the attached claims.

Claims

CLAIMS:
1. A phase locked loop comprising: voltage controlled oscillator (VCO) means (6) having an input and an output, wherein the frequency at said output (fvc0) is responsive to an input voltage (V,) at said input; phase detector means (2) with a first input for receiving a reference signal (fREF) and a second input for receiving a signal from said output of said
VCO means (6), for generating a set of output signals indicating whether the frequency at said first input is higher or lower than the frequency at said second input; filter means (4) operationally connected to said phase detector means
(2), said said filter means (4) being arranged to convert said set of output signals of said phase detector means (2) into a substantially DC voltage, said substantially DC voltage being operationally connected to the input of said VCO means (6); c h a r a c t e r i z e d in that said phase locked loop also comprises: control means (7) having at least one input responsive to signals indicating whether said frequency (fvco) at the output of said VCO means (6) is higher or lower than the frequency of said reference signal (fREF); and at least one output signal for controlling the input voltage (Vt) to said VCO means (6); an adjustable control element (5), which is arranged to control the frequency of said VCO means (6) and responsive to said output signal from said control means (7); means for receiving a reference voltage (VREF); selector means (SW1) capable of selectively connecting, under the control of said control means (7), the input of said VCO means (6) to said reference voltage (VREF).
2. Phase locked loop according to claim ^ c h a r a c t e r i z e d in that said phase detector means (2) comprises a first output (U) which is responsive to the frequency at said first input being higher than the frequency at said second input; and a second output (D) which is responsive to the frequency at said first input being lower than the frequency at said second input; and said control means (7) comprises a first input connected to said first output (U) of said phase detector means (2) and a second input connected to said second output (D) of said phase detector means (2).
3. Phase locked loop according to claim 1 or 2, characterized in that said phase locked loop also comprises comparison means (8) having at least two inputs and at least one output, said comparison means (8) being arranged to compare said substantially DC voltage produced by said filter means (4) to said reference voltage (VREF) and said at least one output of said comparison means (8) being operationally connected to said inputs of said control means (7).
4. Phase locked loop according to any one of the claims 1 - 4, characterized in that said adjustable control element (5) comprises an electrically adjustable potentiometer (EPOT).
5. Phase locked loop according to any one of the claims 1 - 4, characterized in that said adjustable control element (5) comprises a sample and hold circuit connected to a voltage controlled amplifier.
6. Phase locked loop according to any one of the claims 1 - 4, characterized in that said adjustable control element (5) comprises a resistor matrix consisting of resistors and analogue switches.
7. Phase locked loop according to any one of the preceding claims, characterized in that said phase locked loop is installed in a base station of a cellular communications system and said control means (7) further comprises input means (EN) permitting the base station to enable the control means (7).
8. Phase locked loop according to any one of the preceding claims, characterized in that said control means (7) further comprises an output signal (RDY) indicating that the frequency of said oscillator means (6) is within a predetermined deviation from its nominal value.
9. Method for adjusting the frequency of a phase locked loop wherein said phase locked loop comprises: a voltage controlled oscillator (VCO) (6) having an input and an output wherein the frequency (fvco) at said output is responsive to an input voltage (Vt) at said input; a phase detector (2) comprising a first input for receiving a reference signal (fREF) and a second input for receiving a signal from said output of said VCO (6), and comprising a set of outputs indicating whether the frequency at said first input is higher or lower than the frequency at said second input; a filter (4) operationally connected to the set of outputs of said phase detector (2) and converting the signal therein into a substantially DC voltage, said DC voltage being operationally coupled to the input of said VCO (6); and characterized in that said method comprises the following steps: receiving a reference voltage (VREF); connecting the input of said VCO (6) to said reference voltage (VREF); adjusting an adjustable element (5) within said phase locked loop; reconnecting said input of said VCO (6) to receive said substantially DC voltage produced by said filter means (4).
10. Method according to claim 9, characterized in that said method for adjusting is initiated upon detecting an active enable signal (EN) from outside the phase locked loop.
11. Method according to claim 10, characterized in that said method further comprises the step of producing a ready signal (RDY) indicating that the frequency (fvco) at the output of said oscillator means (6) is within a predetermined deviation from its nominal value.
12. Method according to claim 9, characterized in that said step of adjusting is terminated upon detecting a predetermined period of time when no output signals originate from said phase detector (2).
13. Method according to claim 10, characterized in that said step of adjusting is terminated upon detecting an inactive enable (EN) signal from outside the phase locked loop.
PCT/FI1997/000691 1996-11-15 1997-11-13 Apparatus and method for stabilising the frequency of a phase locked loop WO1998023034A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU50528/98A AU5052898A (en) 1996-11-15 1997-11-13 Apparatus and method for stabilising the frequency of a phase locked loop

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9623872.0 1996-11-15
GB9623872A GB2319409B (en) 1996-11-15 1996-11-15 Apparatus and method for stabilising the frequency of a phase locked loop

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WO1998023034A2 true WO1998023034A2 (en) 1998-05-28
WO1998023034A3 WO1998023034A3 (en) 1998-07-30

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Publication number Priority date Publication date Assignee Title
EP2135353A1 (en) * 2006-12-04 2009-12-23 ITS Electronics Inc. Floating dc-offset circuit for phase detector

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2135353A1 (en) * 2006-12-04 2009-12-23 ITS Electronics Inc. Floating dc-offset circuit for phase detector
EP2135353A4 (en) * 2006-12-04 2012-10-10 Its Electronics Inc Floating dc-offset circuit for phase detector

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Publication number Publication date
GB9623872D0 (en) 1997-01-08
WO1998023034A3 (en) 1998-07-30
GB2319409A (en) 1998-05-20
GB2319409B (en) 1999-01-27
AU5052898A (en) 1998-06-10

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