GB2317280A - Bandwidth adjustment in phase locked loops - Google Patents

Abstract

A phase locked loop is provided with a digitally implemented loop filter 14 comprising an analogue to digital converter 22 for converting a phase error signal to a discrete time phase error signal, a digital filter e.g. a signal processor 22, for filtering the phase error signal and a digital to analogue converter 24 for converting the filtered phase error signal into a continuous time phase error signal. By providing the phase locked loop with a digital loop filter, a loop bandwidth of the phase locked loop may be adjusted by arranging for the impulse response coefficients of the digital filter to be changed, thereby effecting a change in the loop bandwidth with substantially reduced noise. The signal processor 22 may be controlled by a control circuit 26 and an associated data store 28. The phase lock loop may form part of a frequency hopping radio transmitter or receiver.

Description

IMPROVEMENTS IN OR RELATING TO PHASE LOCKED LOOPS The present invention relates to phase locked loops.

In signal processing apparatus, such as that used in radio receivers and transmitters, it often required to synchronise one sinusoid to another. A phase locked loop is a known apparatus for synchronising one sinusoid to another.

A diagram of a phase locked loop, which operates to phase lock an output signal fO to an input signal fi is shown in Figure 1.

In Figure 1, fi is fed to a mixer 1, which serves to generate signals representative of a multiplication of fi by a signal fed back from an output of a voltage controlled oscillator 2. The signals representative of the multiplication are thereafter fed from an output of the mixer 1 to a low pass filter 3, which operates to filter the multiplied signals such that at an output of the low pass filter 3, there is provided signals representative of a phase error between the input signal fi and the output signal fo. The output of the low pass filter 3 is connected to an input of the voltage controller oscillator 2. As a result, the voltage controlled oscillator 2, operates to adjust the frequency of the output signal fO in accordance with the phase error thereby acquiring phase lock of the output signal fO to the input signal fi. In combination, the mixer 1 and low pass filter 3 operate to form a phase sensitive detector by multiplying the output signal fo by the input signal fi and attenuating high frequency harmonics resulting from the multiplication, thereby separating the phase error component corresponding to low frequency signals from the high frequency harmonics in accordance with the well documented operation of the phase locked loop shown in Figure 1.

A loop bandwidth of the phase locked loop is determined by the bandwidth of the low pass filter 3. The loop bandwidth is arranged to be wide enough to allow the phase locked loop to track a change in the input frequency fi and respond by introducing a corresponding change in the phase of the output frequency fo, and small enough to reject any noise components introduced in the signals represented at the output of the mixer 1.

In known phase locked loops, the low pass filter is a lead lag analogue filter, comprising an arrangement of passive components.

In some applications, it is a requirement that a phase locked loop be used which is provided with a means for tracking, or phase locking, the output signal fo to the input signal fi, wherein the frequency of the input signal fi may change over a predetermined bandwidth at a given time. With such a requirement, a problem arises in providing a low pass filter with a bandwidth low enough to attenuate harmonic and noise components introduced by the mixer 1, whilst being wide enough to provide for rapid changes in the frequency of the output signal fo, in accordance with corresponding changes in the frequency of the input signal fi, so as to obtain phase lock of the output signal fO to the input signal fi.

This problem is addressed in known phase locked loops by incorporating a second low pass filter which is arranged to be switched into and out of the loop in place of the first low pass filter, and wherein the first low pass filter is arranged to have a low cut off frequency to reject noise components from the mixer 1, whereas the second low pass filter is arranged to have a higher cut off frequency, thereby providing a high loop bandwidth, with which the phase locked loop may rapidly track the new frequency of the input signal fi and acquire phase lock. Once phase lock has been acquired the second low pass filter is switched out of loop and the first low pass filter is switched into the loop, thereby rejecting a larger amount of noise power from the loop in accordance with a substantially reduced loop bandwidth.

A problem with such known phase locked loops, is that at a point where the first filter is switched out and the second filter switched into the loop, noise signals are induced into the loop, thereby causing phase offsets and noise to be added to the output signal fo.

Accordingly, it is an object of the present invention to provide a phase locked loop, wherein the aforementioned disadvantages of known phase locked loops are obviated.

According to the present invention there is provided a phase locked loop comprising a phase sensitive detector which operates to generate an error signal representative of a phase difference between a first signal and an output signal, a loop filter being connected to the phase sensitive detector which operates to filter the error signal, and a voltage controlled oscillator which operates to generate the output signal, a frequency of which output signal is selectively controlled in accordance with the error signal fed thereto, characterised in that the loop filter comprises an analogue to digital converter which operates to convert the error signal into a discrete time representation of the error signal, a digital filter which operates to filter the said discrete time error signal, and a digital to analogue converter which thereafter converts said discrete time filtered error signal into a continuous time filtered error signal fed to the voltage controlled oscillator.

By providing an analogue to digital converter, and a digital to analogue to converter between the phase sensitive detector of the phase locked loop and the voltage controlled oscillator, the phase error signal generated by the phase sensitive detector may be processed in the digital domain. As such, by providing a digital filter, the phase error signal may be filtered in the digital domain, and the loop bandwidth will be determined in accordance with the impulse response coefficients of the digital filter. By selectively controlling the impulse response coefficients of the digital filter, the phase locked loop is provided by a means whereby it can switch between high and low cut off frequencies in combination with a requirement of the phase locked loop to track a frequency change in the input signal.

The phase locked loop may further be provided with a phase locked loop controller which operates to adapt the impulse response coefficients of the digital filter in accordance with a change in the frequency of the input signal which the phase locked loop is required to track.

The phase locked loop may be embodied within a frequency synthesiser which is provided with a means for generating an output signal with one of a plurality of selectable frequencies in accordance with a reference signal with a predetermined frequency, wherein the phase locked loop operates to change the loop bandwidth in accordance with changes in the frequency of the output signal.

One embodiment of the present invention will now be described by way of example only, wherein FIGURE 2 is a phase locked loop frequency synthesiser.

In an application such as frequency hopping radio, the radio is required to switch rapidly between a number of predetermined channels and yet maintain low levels of noise and spurious signals.

In such applications a phase locked loop is used. An embodiment of the present invention will thereby be illustrated with reference to a frequency hopping application, wherein a synthesiser is required to change frequencies over a number of predetermined frequencies, although as will be appreciated, application of the present invention may be to any signal processing apparatus, wherein a phase locked loop is required to respond rapidly to changes in a frequency to which the loop is required lock.

Figure 2 provides a block diagram illustration of a phase locked loop frequency synthesiser.

In Figure 2 a reference frequency generator 6, generates a reference signal which is fed to a frequency divider 8. The frequency divider 8 operates to divide the frequency of the reference signal by a predetermined parameter R, and thereafter to feed the divided signal to a positive input of a phase sensitive detector 10. A negative input of the phase sensitive detector 10 is fed by an output signal of the frequency synthesiser via a second frequency divider 12. The second frequency divider 12 operates to divide the output signal by a parameter N. An output of the phase sensitive detector 10 is fed to an input of a digital loop filter 14, an output of which is fed to a voltage controlled oscillator 16.

The output of the voltage controlled oscillator 16 serves to generate an output signal of the frequency synthesiser at a conductor 18.

In operation, the frequency synthesiser serves to generate an output signal with a frequency determined in accordance with the frequency of the reference signal generated by the reference signal generator 6, the first frequency divider 8, and the second frequency divider 12. The frequency synthesiser is arranged to provide an output signal on conductor 18 with a frequency which is arranged to hop over a predetermined set of frequencies. A displacement between those frequencies is determined by the relationship between the parameters R and N of the first and second frequency dividers and the frequency of the reference signal fref. This relationship is as given in equation 1.

25kHz = fo = fret (1) N R So for example where the change of frequency is in this case the frequency displacement 25KHz, then the values of N and R are determined with reference to the frequency of the reference frequency generated by the reference frequency generator 6 such that equation 1 is satisfied. By changing the parameters N and R, the frequency synthesiser is arranged to generate the output signal with the predetermined frequencies. The phase locked loop frequency synthesiser operates thereafter in a similar fashion to the phase locked loop hereinbefore described. The phase sensitive detector 10, may be a mixer as described with Figure 1, and arranged to generate a phase error between the signal at the negative input as compared to the signal presented at the positive input. The phase error is thereafter filtered by the digital loop filter before being applied to the input of the voltage controlled oscillator 16. The digital loop filter thereby provides the loop bandwidth of the phase locked loop.

The digital loop filter 14, is shown in Figure 2 to be comprised of an analogue to digital converter 20, connected to a data processor 22, an output of which is thereafter connected to a digital to analogue converter 24. The analogue to digital converter operates to convert the continuous time error signal generated by the phase sensitive detector 10, into a discrete time representation of the phase error signal in accordance with a predetermined sampling rate and a predetermined resolution of the digital samples represented as a number of bits. The resolution of the digital samples is determined in accordance with a requirement for a minimum level of quantisation noise in combination with the frequency displacement AF of the hop frequencies required to be generated by the frequency synthesiser. For a frequency displacement aF = 25kHz, the resolution of digital samples should be in the order of sixteen bits.

The discrete time phase error signal is thereafter filtered by the data processor 22, and the filtered signal is thereafter fed to the digital to analogue converter 24 which converts the discrete time filtered phase error signal into a continuous time filtered phase error signal fed to the input of the voltage controlled oscillator 16.

The data processor 22, therefore provides the digital filtering operation of the loop low pass filter. The digital filtering performed by the data processor 22, may be of an infinite impulse response type or may be a finite impulse response filter type.

When the frequency synthesiser is required to hop the synthesised signal to a new frequency, the loop bandwidth should be wide enough to allow rapid settling of the phase locked loop to track the phase of the signal at the new frequency whilst being narrow enough to reject noise present in the phase locked loop as hereinbefore described. To provide a means whereby the phase locked loop has a wide loop bandwidth whilst the frequency synthesiser is hopping to a new frequency, and a narrow loop bandwidth after the frequency synthesiser has phase locked to the new frequency, the digital filter embodied within the data processor 22 is provided with a set of impulse response coefficients which are selectively adapted in accordance with the loop bandwidth required. To this end a control unit 26 operates to adjust the taps of the digital filter within the data processor 22 in accordance with changes in the frequency of the output signal from the frequency synthesiser. This may be achieved by providing a data store 28 for storing a plurality of sets of impulse response coefficients which are selectively exchanged with the impulse response coefficients of the digital filter presently embodied within the data processor 22.

The voltage controlled oscillator 16 is an analogue component which is required to provide a substantially linear change in the frequency of the output signal in accordance with voltage levels applied to the input. However, where the frequency synthesiser is required to hop over a wide range of predetermined frequencies, it is difficult to provide a voltage controlled oscillator with a substantially linear voltage to frequency relationship. By providing a set of impulse response coefficients for the digital filter embodied within the data processor 22, which impulse response coefficients are arranged to compensate for any nonlinearity in the voltage to frequency relationship of the voltage controlled oscillator 16, a combination of the digital loop filter 14, and voltage controlled oscillator 16, provides the phase locked loop with a substantially linear voltage to frequency relationship.

As hereinbefore mentioned, for a displacement frequency hop of 25KHz, a resolution in the digital samples of the digital loop filter may be required to be sixteen bits. However, the analogue to digital converter 22 and digital to analogue converter 24, may be implemented in combination with the digital filter embodied within the data processor unit 22, in accordance with Sigma-Delta conversion, wherein the resolution of the discrete time signal samples is only one bit. To compensate for the reduction in resolution, the phase error signal is substantially over sampled in accordance with the corresponding reduction in resolution of the discrete time samples. This would therefore provide the digital loop filter 14 with a comparatively simple architecture and structure which would serve to the reduce cost of implementing the digital loop filter 14.

Since the loop filter to be implemented is of a relatively simple lead lag network type, with perhaps one or two additional poles, the digital filter could be implemented as an Applications Specific Integrated Circuit (ASIC) rather than a general purpose Digital Signal Processor (DSP). This would provide a substantial power and cost saving.

As will be appreciated by those skilled in the art, various modifications may be made to the arrangements and embodiment of the phase locked loop whilst still falling within the scope of the present invention. In particular, the phase locked loop structure comprising a digital filter may be applied to a wide range of signal processing applications, such as in a tuneable receiver for radio signals.

Claims (11)

1. A phase locked loop comprises a phase sensitive detector which operates to generate an error signal representative of a phase difference between a first signal and an output signal of the phase locked loop, a loop filter being connected to the phase sensitive detector which operates to filter the phase error signal, and a voltage controlled oscillator which operates to generate the output signal, a frequency of which output signal is determined in accordance with the phase error signal, characterised in that the loop filter comprises an analogue to digital converter which operates to convert the phase error signal into a discrete time representation of the phase error signal, a digital filter which operates to filter the said discrete time error signal, and a digital to analogue converter which thereafter converts the said discrete time filtered phase error signal into a continuous time filtered phase error signal fed to the voltage controlled oscillator.

2. A phase locked loop as claimed in Claim 1, wherein the loop filter further comprises a data store which serves to store a plurality of sets of impulse response coefficients and a filter controller which operates to selectively switch the impulse response coefficients of the digital filter with one of the said plurality of sets of impulse response coefficients.

3. A phase locked loop as claimed in Claim 2, wherein the filter controller operates to selectively switch the impulse response coefficients of the filter in accordance with a change in frequency of the output signal.

4. A phase locked loop as claimed in Claim 3, wherein the impulse response coefficients are arranged to be determined in dependence upon a frequency response characteristic of the voltage controlled oscillator and a frequency of the output signal, so as to provide a substantially linear voltage to frequency relationship of the voltage controlled oscillator in combination with the loop filter over a range of predetermined frequencies.

5. A phase locked loop as claimed in any preceding Claim, wherein the analogue to digital converter and digital to analogue converter are of a Sigma-Delta type.

6. A phase locked loop as claimed in Claim 5, wherein the digital samples of the said discrete time phase error signal have a resolution of one bit, and the digital filter operates to filter one bit samples.

7. A phase locked loop as claimed in any preceding Claim, wherein the digital filter is a finite impulse response filter.

8. A phase locked loop as claimed in any preceding Claim, wherein the digital filter an infinite impulse response filter.

9. A phase locked loop as claimed in any preceding Claim, wherein the phase frequency detector is a signal mixer.

10. A frequency synthesiser comprising a phase locked loop as claimed in any preceding Claim.

11. A phase locked loop as hereinbefore described with reference to Figure 2.