EP0454917A1

EP0454917A1 - Frequency synthesiser

Info

Publication number: EP0454917A1
Application number: EP90304758A
Authority: EP
Inventors: David Stockton
Original assignee: Hewlett Packard Ltd
Current assignee: Hewlett Packard Ltd
Priority date: 1990-05-02
Filing date: 1990-05-02
Publication date: 1991-11-06
Anticipated expiration: 2010-05-02
Also published as: DE69011670D1; DE69011670T2; EP0454917B1

Abstract

A frequency synthesiser has a frequency multiplier such as a phase locked loop (20) for providing a required output frequency. A reference frequency source is coupled to a first direct digital synthesiser (11) and a reference loop (14) couples the first synthesiser (11) to the multiplier (20). The loop (14) including a second direct digital synthesiser (15). The two direct digital synthesisers (11 and 15) operate in a reciprocal manner such that the 2ⁿ values in their multiplication factors cancel. The parameters of the various elements can be arranged such that the output frequency is directly related to the multiplication factor of the first direct digital synthesiser (11).

Description

This invention relates to frequency synthesisers.
There are many applications in which there is a requirement for a frequency synthesiser capable of providing signals having a highly stable frequency which can be varied in finite steps over a specified range. There are several different types of frequency synthesiser which attempt to achieve this objective.
One known frequency synthesiser employs a phase-locked loop the reference signal for which is provided by a voltage controlled crystal oscillator. In the case of a digitally controlled phase locked loop the divider of the loop can be adjustable under microprocessor control to give range of frequencies at the output of the loop. Additionally the output of the crystal oscillator can be adjusted to provide additional output values between the coarse values provided by varying the division ratio of the loop. The resolution at the output of the loop can be improved by providing a further variable divider between the voltage controlled oscillator and the phase sensitive detector of the loop. Frequency synthesisers using phase locked loops can provide high frequency operation, but where fine resolution is required over the frequency range of the output this is difficult and expensive to achieve.
It is also known to generate signals by direct digital synthesis. Synthesisers using direct digital synthesis offer fine resolution, but the maximum frequency of their operation is limited. Their output has good phase noise, but quantisation distortion components are created.
Attempts have been made to provide frequency synthesisers which make use of a combination of direct digital synthesis and phase locked loop techniques. One such synthesiser uses a direct digital synthesiser as the reference signal source for a phase locked loop frequency multiplier. A problem with such an arrangement is that the phase locked loop magnifies any quantisation components from the direct digital synthesiser which lie within its bandwidth. Additionally direct digital synthesisers are usually implemented in binary arithmetic and act as frequency multipliers where the multiplication factor is of the form x/2ⁿ. This means that the step size resolution is the frequency of the input to the direct digital synthesiser divided by 2ⁿ. If n is not zero then 2ⁿ is not a convenient decimal number. This makes it impossible to have a convenient round decimal value for both the input frequency to the direct digital synthesiser and the step size. This is inconvenient for users of frequency synthesisers.
The present invention is concerned with the frequency synthesiser which employs direct digital synthesis and phase locked loop techniques and which minimises the problems outlined above.
According to the present invention there is provided a frequency synthesiser comprising a frequency multiplier for providing the required output frequency, a reference frequency source coupled to a first direct digital synthesiser and a reference loop coupling the first direct digital synthesiser to the frequency multiplier, said reference loop including a second direct digital synthesiser, the arrangement being such that the synthesisers operate in a reciprocal manner whereby the 2ⁿ values in thier multiplication factors can be made to cancel.
The invention will be described now by way of example only with particular reference to the accompanying drawings. In the drawings:

Figure 1 is a block schematic diagram of a frequency synthesiser in accordance with the present invention, and
Figure 2 is a block schematic diagram similar to Figure 1 but showing some of the elements in more detail.

Referring to Figure 1 a frequency synthesiser comprises an input 10 to which is applied the output signal f_s of a frequency standard. The input 10 is connected to a first direct digital synthesiser 11 which has a multiplication factor of A/2^na. A is an integer used to control the frequency output from the synthesiser and na is the number of bits used in the synthesiser arithmetic. The output of the synthesiser 11 is applied to the phase sensitive detector 12 of a reference loop 14. In addition to the phase sensitive detector 12 the loop 14 includes a second direct digital synthesiser 15 (shown as having a multiplication factor B/2^nb), an integrator 16 and a voltage controlled oscillator 18. The loop 14 provides a reference signal for a frequency multiplier 20, the reference signal being applied to the frequency multiplier 20 by way of a divider 21. The frequency multiplier 20 can be a phase locked loop. The output of the multiplier 20 is the required output frequency f_o.
Considering the operation of the circuit shown in Figure 1 the output of the direct digital synthesiser 11 is a signal of frequency

The frequency of the signal at point x on Figure 1 is

The frequency of the signal at the output divider 21 is

The frequency at the output of the multiplier 20 is given by

Thus it can be seen that if the accumulator size of each of the direct digital synthesisers 11 amd 15 is made the same, i.e. na=nb, the factors 2^na and 2^nb cancel in the expression for f_o. Thus f_o is given by
This cancellation thus removes the usual problem of direct digital synthesisers, namely that of providing a convenient step size. With the arrangement described above it is possible to use a reference source having a round figure frequency value, e.g. 10 MHz. If B is made a fixed multiple of D then the effect of D on the step size contribution of the DDS system can be cancelled.
Referring to Figure 2 this shows in slightly more detail a frequency synthesiser of the general form shown in Figure 1. In this arrangement the output frequency mutliplier 20 comprises a phase locked loop having a phase sensitive detector 31, an integrator 32, a loop oscillator 33 and a divider 34. The division factor N of the divider can be adjusted.
As shown in Figure 2 each direct digital synthesiser has associated with it a digital to analoge converter 40, 41 and a low pass filter 42, 43. The oscillator 18 in the loop 14 is a crystal controlled oscillator whose output frequency can be varied slightly in a conventional manner.
It will be appreciated that an arrangement of the form shown in Figure 2 can be controlled by a conventional microprocessor to provide a desired output frequency.
By appropriate selection of parameters it is possible to simplify programming of such an arrangement. Consider the following example
Let 2^na = 2^nb = 2³²= 4,294,967,296
Let f_o = 10 MHz
Let VCXO output frequency be 10 MHz ± 1000 ppm
Let f_o cover 500-1000 MHz in 1Hz steps
Let C = 10
Let A_maximum = B_maximum =2³⁰
Let N = 500-1000
Let B = N X 1,000,000 (so B=500,000,000 to 1,000,000,000 and 2³⁰=1,073,741,824)
The output frequency f_o is given
Thus it can be seen by appropriate selection of the parameters in the expression for the output frequency, the output frequency is simply a function of the value loaded into the direct digital synthesiser 11. In the example given the phase sensitive detector 12 of the reference loop 14 runs at 1.25 to 2.5 MHz. This means that the two synthesisers 11 and 15 are in their optimum operating regions. In order to program such an arrangement all that is required is to carry out the following steps:

1. Select the nearest integer of the required output frequency expressed in MHz, load this as value N into the divider 34 of the phase locked loop 20.
2. Load 1,000,000 x N into the B section of the direct digital synthesiser 15.
3. Load the required frequency value in Hz into the A section of the digital synthesiser 11.

It will be appreciated that the above example applies for any output frequency f_o in the range 500 MHz to 1000 MHz.
The synthesiser structure described above has a number of advantages. Firstly it enables the use of a frequency standard of a round decimal value (e.g. 10 MHz) as the frequency source applied to input 10 and still makes it possible to achieve round decimal (e.g. 1 Hz) step sizes in the output frequency even though the synthesiser uses binary arithmetic digital direct synthesisers. Secondly a constant step size is achieved across the output range without gaps. Thirdly the slow loop 14 acts as a narrow tracking filter effectively removing the quantising noise created by the use of direct digital synthesisers. The slow loop also removes any phase noise of the reference source thus eliminating the need for a separate clean-up loop which is usually required in conventional synthesisers making use of phase locked loops.
Additionally if required frequency modulation can be applied to the crystal controlled oscillator. Also digital to analogue converters can be used to pre-tune the crystal controlled oscillator 18 and the voltage controlled oscillator 33 in the phase locked loop thus speeding up lock acquisition.
It will be appreciated that where a sine wave output is required the output from the frequency multiplier is applied to a suitable filter structure.

Claims

A frequency synthesiser comprising a frequency multiplier for providing a required output frequency, a reference frequency source coupled to a first direct digital synthesiser, and a reference loop coupling the first direct digital synthesiser to the frequency multiplier, said reference loop including a second direct digital synthesiser, the arrangement being such that the synthesisers operate in a reciprocal manner whereby the 2ⁿ values in their multiplication factors can be made to cancel.
A frequency synthesiser according to claim 1, wherein the frequency multiplier is a phase locked loop.
A frequency synthesiser according to claim 2, wherein the phase locked loop includes a divider whose division ratio can be varied.
A frequency synthesiser according to any preceding claim, wherein the multiplication factor of the second direct digital synthesiser has a selected relationship with the multiplication factor of the frequency multiplier.
A frequency synthesiser according to claim 4, wherein the multiplication factors of the first and second direct digital synthesiser and the frequency multiplier are selected such that the output frequency is directly related to multiplication factor of the first direct digital synthesiser.
A frequency synthesiser according to any preceding claim, wherein said reference loop includes a voltage controlled crystal oscillator.
A frequency synthesiser according to any preceding claim, including a divider coupling the reference loop to the frequency multiplier.
A frequency synthesiser according to any preceding claim, including a microprocessor for adjusting the multiplication factors of the first and second direct digital synthesiser and the frequency multiplier to provide the required output frequency.