GB9618986D0 - Improvements in or relating to phase locked loops - Google Patents
Improvements in or relating to phase locked loopsInfo
- Publication number
- GB9618986D0 GB9618986D0 GBGB9618986.5A GB9618986A GB9618986D0 GB 9618986 D0 GB9618986 D0 GB 9618986D0 GB 9618986 A GB9618986 A GB 9618986A GB 9618986 D0 GB9618986 D0 GB 9618986D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- relating
- phase locked
- locked loops
- loops
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/713—Spread spectrum techniques using frequency hopping
- H04B1/7136—Arrangements for generation of hop frequencies, e.g. using a bank of frequency sources, using continuous tuning or using a transform
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9618986A GB2317280A (en) | 1996-09-11 | 1996-09-11 | Bandwidth adjustment in phase locked loops |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9618986A GB2317280A (en) | 1996-09-11 | 1996-09-11 | Bandwidth adjustment in phase locked loops |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9618986D0 true GB9618986D0 (en) | 1996-10-23 |
GB2317280A GB2317280A (en) | 1998-03-18 |
Family
ID=10799781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9618986A Withdrawn GB2317280A (en) | 1996-09-11 | 1996-09-11 | Bandwidth adjustment in phase locked loops |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2317280A (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004052416B4 (en) * | 2004-10-28 | 2012-05-10 | Infineon Technologies Ag | Loop filter |
US7696829B2 (en) * | 2006-09-21 | 2010-04-13 | Infineon Technologies Ag | Frequency synthesizer and method |
EP2009796A1 (en) * | 2007-06-28 | 2008-12-31 | Alcatel Lucent | Method for filtering a signal in a phase-locked loop, phase locked loop, base station and communication network therefor |
GB0800251D0 (en) | 2008-01-08 | 2008-02-13 | Zarlink Semiconductor Inc | Phase locked loop with adaptive filter for dco synchronization |
WO2009156450A1 (en) * | 2008-06-27 | 2009-12-30 | Thomson Licensing | Temporal adjustment of the cut-off frequency of a packet reception device connected to a network |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI93286C (en) * | 1993-03-08 | 1995-03-10 | Nokia Telecommunications Oy | Method of forming a clock signal with a phase-locked loop and phase-locked loop |
CA2130871C (en) * | 1993-11-05 | 1999-09-28 | John M. Alder | Method and apparatus for a phase-locked loop circuit with holdover mode |
-
1996
- 1996-09-11 GB GB9618986A patent/GB2317280A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2317280A (en) | 1998-03-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |