WO1994021047A1

WO1994021047A1 - Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Info

Publication number: WO1994021047A1
Application number: PCT/FI1994/000076
Authority: WO
Inventors: Esa Laaksonen
Original assignee: Nokia Telecommunications Oy
Priority date: 1993-03-08
Filing date: 1994-03-03
Publication date: 1994-09-15
Also published as: FI931019A0; FI93286C; GB9518446D0; DE4491210T1; GB2291548B; AU6143094A; FI931019A; FI93286B; GB2291548A

Abstract

The invention relates to a method of generating a clock signal (CLK) by means of a phase-locked loop comprising a phase comparator (101), a loop filter (102), and a voltage-controlled oscillator (105), wherein a synchronizing signal (MCLK) derived from a synchronization source is applied to a first input in the phase comparator (101) and the clock signal is locked to the synchronizing signal, the locking of the loop being speeded up by increasing the bandwidth of the loop. In order that unnecessary changes in the clock frequency could be prevented and necessary changes could be speeded up, changes in a control voltage (Vc3) of the oscillator (105) are prevented temporarily in response to a change where a currently applied synchronizing signal becomes inadequate for use in timing, and the bandwidth of the loop is increased temporarily in response to a change where a synchronizing signal adequate for use in timing is again taken into use.

Description

Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

The invention relates to a method according to the preamble of the attached claim 1 for generating a clock signal by means of a phase-locked loop, and to a phase-locked loop according to the preamble of the attached claim 5. The method and the phase-locked loop according to the invention can be applied primarily in slave oscillators of digital telecommunication systems, i.e. oscillators intended to be locked to the master clock signal of the system.

In present-day digital transmission systems, synchronization can be performed by the use of either separate synchronizing connections or normal data connections between system nodes ( evices). Separate synchronizing connections are used only in individual cases and very seldom for the synchronization of the entire network. When data connections are used for synchronization, the line code should be such that even the clock frequency can be extracted from an incoming data signal by the nodes. These clock fre¬ quencies allow the synchronization of network nodes to be performed by two different basic methods: mutual synchronization and master-slave synchronization. In mutual synchronization each node derives its own clock frequency from the average value of the frequencies of incoming signals and its own current clock frequency. In this way, all nodes in the network are driven towards a common average frequency, and achieve it in stable state. However, a network utilizing mutual synchronization cannot be synchronized with a desired source, so that it is problematic to interconnect e.g. different networks, as the operating frequency of the entire network cannot thereby be accurately determined in advance. In master-slave synchronization, instead, all network nodes are synchronized with the clock frequency of a specific node called a master node. Each node selects the frequency of a single incoming signal as the source of its own clock frequency. The node tends to select a signal having the clock frequency of the master node of the network.

In independent master-slave synchronization, each node makes the synchronization decision in- dependently without any external information support¬ ing the decision making. As the nodes make their synchronization decision independently, each node has to contain specifications defining the node with which this node should be synchronized. These specifications are often in the form of a priority list, and the node selects the signal of the highest priority from amongst incoming signals of adequate quality as its source of synchronization. If the signal breaks or its quality deteriorates so that it is no longer adequate for use as a source of synchronization, the node selects the signal having the next highest priority from the list. The priority list has to be selected so that all nodes contained in it are located between the concerned node and the master mode, so that the syn- chronization will be distributed from the master node to the lower levels.

Independent master-slave synchronization, how¬ ever, imposes limitations on synchronization: in a loop network all connections cannot be used for syn- chronization, whereby the dynamic adaptability of the network in different situations is limited. Internodal communication has to be established to ensure that each individual node has enough information for de¬ cision making in all situations without having to drastically limit the number of connections available for synchronization, whereby the clock frequency of the master node could not be equally efficiently distributed to the network nodes in failure situ¬ ations. Loop protected ( P) synchronization is the simplest method of making independent master-slave synchronization more communicative. LP synchronization aims to prevent the losing of timing in loop networks by using, in addition to the above-mentioned priority lists, two state bits mcb and lcb transmitted between network nodes. The first state bit mcb (master control bit) indicates whether the network synchronization originates from the master node of the network. The master node defined for the network transmits this bit as a logic zero in its outgoing signals, and other nodes forward it if they are synchronized with a signal in which the value of the mcb bit is zero. The second state bit lcb (loop control bit) indicates whether a loop is formed in synchronization. Each network node transmits this bit as a logic one in the direction in which it is synchronized itself, and as a logic zero in all other directions.

Each node uses its own priority list on select¬ ing its source of synchronization, but it checks not only the state of the signal but also the mcb and lcb bits before making the selection. In the first place, the node aims to find a connection having a clock frequency originating from the master node of the network (mcb=0). If such a connection cannot be found (due to a failure situation), the node selects, as normal, an operative connection having the highest priority. However, it is always required from the selected connection (the source of timing) that its timing is not in a loop (lcb=0), even though the signal itself would otherwise be of adequate quality for synchronization.

In order that the heavy specifications of the LP synchronization (which usually still have to be changed when nodes are added to or removed from the network) could be avoided, internodal communication should be extended from two state bits to messages. In this kind of message-based master-slave synchroniza¬ tion the node is able to make the decision concerning its own synchronization on the basis of synchronizing messages contained in incoming signals. No priority list is thereby needed, and all network connections can be used for synchronization. The synchronizing message contains all synchronization information required by the node. The node has to know the origin of the synchronization of the signal containing the synchronizing message in order that it would be syn¬ chronized with a clock frequency originating from the master node of the network. The messages also have to contain sufficiently other information in order that the node could select the best one from available alternatives, and in order that synchronization loops would not be formed. One prior art message-based synchronization method is the SOMS (Self-Organizing Master-Slave Synchronization) method, which is de- scribed more fully e.g. in Finnish Patent Applications 925 070 - 925 074. Message-based synchronization methods are also described in US Patents 2,986,723 and 4,837,850.

The method and phase-locked loop according to the present invention are intended for use in tele¬ communication networks utilizing synchronization methods of the type described above, where a network node has to synchronize with the master clock signal of the network. A problem with these networks is that differ- ences are created between the clock frequencies of different devices (nodes) of the network in connection with changes in the synchronization source. Such changes may be e.g. a failure of the master clock source or a break in connections between some network portions. When the network portions operate at dif¬ ferent clock frequencies, bit error bursts occur between them. The number of bursts is the higher the greater the difference between the clock frequencies. Traditionally the oscillators of digital trans¬ mission systems have been switched to free oscillation in the absence of an incoming master clock. A change in the network timing thereby causes two changes in the synchronization source of the oscillator, and between the changes there is a period during which the oscillator is not locked to any external timing source. At the production stage, free oscillation is attempted to be adjusted to the nominal centre frequency. This method, however, does not usually provide any particularly good results, as (i) the properties of the oscillator may vary with time, (ii) the adjustment of the centre frequency is not usually made with any particularly high accuracy, (iii) the master clock frequency may differ from the nominal frequency, and (iv) upon transition of the oscillator from the state of free oscillation to the locked state, or vice versa, there may occur drastic instan¬ taneous frequency changes.

The object of the present invention is to dispense with the above-described drawbacks and to provide a method by means of which devices (nodes) in a digital transmission system are able to flexibly follow changes in the master clock frequency of the network. This is achieved by a method and phase-locked loop according to the invention. The method is charac- terized by what is disclosed in the characterizing portion of the attached claim 1, while the phase- locked loop is characterized by what is disclosed in the characterizing portion of the attached claim 5. The solution according to the invention helps to prevent unnecessary changes in clock frequency and to speed up necessary changes in connection with changes taking place in synchronization, e.g. when the source or route of network synchronization changes. In the following the invention will be described more fully by way of example while referring to Figure 1 of the attached drawings, which is a block diagram illustrating the structure of a phase-locked loop used in the method according to the invention. The phase-locked loop shown in Figure 1 com¬ prises, as is known per se, a phase comparator 101, a lowpass-type loop filter 102 having an input to which an output signal from the phase comparator is con¬ nected, and a voltage-controlled oscillator 105 having its output signal connected to one comparator input in the phase comparator. A master clock signal MCLK originating from the synchronization source (the master node of the network) and obtained from line interface circuits 114 is connected to another co - parator input in the phase comparator. The phase comparator 101 compares the phases of the signals present in its inputs and generates a control signal Vcl proportional to the phase difference between the signals. The control signal is lowpass-filtered in the loop filter 102 into a control signal Vc2. The clock signal CLK of the device (node) is obtained from the output of the voltage-controlled oscillator 105, and, as is well-known, the phase-locked loop tends to control the output signal of the oscillator such that there is no phase difference between the signals present in the comparator inputs of the phase com¬ parator; in other words, the output signal of the oscillator is locked to the frequency of the master clock signal. According to the invention a digital filter block 106 implemented by a processor is integrated in the phase-locked loop on one hand by providing an analog-to-digital converter 103 after the loop filter 102, the output signal of the converter being fed to the filter block, and on the other hand by connecting the output signal of the filter block through a digital-to-analog converter 104 to the input of the voltage-controlled oscillator 105 as the voltage Vc3 controlling the frequency of the oscillator. The filter or processor block 106 comprises a digital lowpass filter 107 having an input to which the output signal of the analog-to-digital converter 103 is connected and subjecting the control signal Vc2, already lowpass filtered once, to additional filtration. The block further comprises a supervision unit 108, a control unit 109 controlled by the super¬ vision unit, and a selector 110 controlled by the control unit 109. The filter block may further have an associated separate control voltage memory 111, which stores the value of the control voltage obtained from the filter 107 in digital form at regular intervals.

In practice, the entire filter block 106 may be implemented by an effective telecommunication pro¬ cessor, whereby the supervision and control units can be implemented entirely by software. The processor may be e.g. of the type 68HC302 or another general-purpose processor of the same level. Instead, it is not advis¬ able to implement the filter block 106 by a signal processor, as the filtration load is light in typical operation. (At present, it is regarded that e.g. a solution where the bandwidth of the prefilter 102 is about 100 Hz, the bandwidth is decreased to 10 Hz, and a slope no greater than 20 dB/decade is needed, is fairly good. A prefilter of greater bandwidth or a greater slope would increase the processor power required for filtration. )

The control signal Vc2 obtained from the analog- to-digital converter 103 in digital form is connected not only to the input of the digital filter 107 but also directly to a first input in the selector 110. The output signal of the digital filter 107 is con¬ nected to a second input in the selector, and the output signal of the memory 111 is connected to a third input in the selector. The output of the selector is connected to the digital-to-analog converter 104.

Furthermore, state and alarm information is connected from the line interface circuits 114 of the device (node) to the input of the supervision unit 108.

It is further to be noted that the phase-locked loop typically comprises (between the oscillator and the phase comparator) a divider, which, however, is not shown in the figure, as it is not relevant to the present invention.

The phase-locked loop according to the invention operates in the following way.

In a normal situation when the clock signal CLK is locked to the master clock signal MCLK originating from the synchronization source, the control signal Vcl from the phase comparator 101 is lowpass-filtered in the loop filter 102. The filtered control signal Vc2 is applied through the analog-to-digital converter 103 to the digital lowpass filter 107, from which it is connected, after further filtration, through the digital-to-analog converter 104 as the voltage Vc3 controlling the frequency of the oscillator 105. In this situation, the control unit 109 has thus controlled the selector 110 into a position in which the input, to which the output signal of the digital lowpass filter 107 is connected, is connected to the output of the selector.

When the supervision unit 108 obtains from the line interface circuits 114 of the device (node) an indication that there is no longer an adequate master clock signal for use as a locking source, the filter block (processor) prevents changes in the control voltage Vc3 as long as locking to the master clock frequency is not possible as the change of the syn- chronization source or route is still in progress. Detection of the need for such prevention is based on state and alarm information obtained from the line interface circuits 114, which may include e.g. the following information: - an alarm indication that a signal is missing from the input interface of the device (node) from which the timing (master clock signal) has been derived, or an alarm indication that the signal of the input interface has deteriorated to such an extent that it can no longer be used for synchronization;

- a change in the state of the LP timing bits such that it is necessary to change the timing source; or

- a change in the state of the SOMS timing mess- age such that it is necessary to change the timing source.

The supervision unit 108 indicates the control unit 109 of the state of change on the basis of the state or alarm information, and the control unit then controls the digital-to-analog converter 104 or the selector 110 on the basis of this information. Change in the control voltage Vc3 of the oscillator is pre¬ vented by freezing the output voltage of the digital- to-analog converter 104 to the value at which it was when the need for prevention was detected. This may be done e.g. by applying a freezing command CTRL by soft¬ ware from the control unit to the digital-to-analog converter 104. If the delays of the supervision system formed by the line interface circuits, the supervision unit and the control unit are so great in the above- described functions that a mere freezing of the output signal of the digital-to-analog converter is too slow to prevent unnecessary frequency changes, the oper¬ ation of the phase-locked loop can be improved by storing the value of the control voltage obtained from the digital lowpass filter 107 in the memory 111 in digital form at regular intervals. The above-mentioned delay of the supervision system determines the time interval between successive stored values. The time interval has to be selected so that it is possible to resume the control voltage that was used when the master clock signal was still adequate. In this case the freezing of the output voltage of the digital-to- analog converter 104 is performed so that the control unit 109 causes the selector 110 to assume a position such that the signal value stored in the memory 111 is connected through the output of the selector 110 directly to the digital-to-analog converter 104.

Freezing the control signal Vc3 (i.e. the oscillator frequency) provides the greatest advantage when the new source of synchronization is the same as previously. In such cases the break may have been caused e.g. by a mere instantaneous disturbance or a change in the route of synchronization in the network. In this way, an unnecessary change of the clock fre- quency is prevented.

When a signal adequate for timing is again found, the filter block 106 (processor) temporarily increases the width of the frequency response of the phase-locked loop. Detection of the need for locking is again based on the state or alarm information obtained from the line interface circuits 114, which may include e.g. the following:

- an alarm indication that an adequate signal is again present in the input interface from which the timing (master clock signal) is to be derived;

- a change in the state of the LP timing bits such that it is necessary to change the timing source; or - a change in the state of the SOMS timing mess¬ age such that it is necessary to change the timing source.

The frequency response can be changed by copying the digital value of the control voltage obtained from the analog-to-digital converter 103 directly to the digital-to-analog converter 104 for a predetermined period. The control unit 109 thus causes the selector 110 to assume a position such that the signal value in the output of the analog-to-digital converter is con- nected through the output of the selector directly to the digital-to-analog converter. In this case, the digital filtration performed in the filter 107 is omitted, so that the bandwidth of the loop of the phase lock increases significantly (increasing the width of the frequency response of the phase lock means that the bandwidth of the lowpass filtration performed by the loop is increased). Increasing the bandwidth in turn speeds up the locking of the loop, which is known per se. The length of the above- mentioned predetermined period, which determines the length of the copying stage, depends on the adjusting speed of the oscillator 105. The minimum duration of the predetermined period should correspond to the maximum of the adjusting period. Upon the expiry of the predetermined period the control unit 109 again causes the selector 110 to assume a position in which the input to which the output signal of the digital lowpass filter 107 is connected, is connected to the output of the selector, whereby the loop again becomes slower.

Even though the invention has been described above with reference to the examples of the attached drawings, it is self-evident that the invention is not limited to them, but it can be modified within the inventive idea disclosed above and in the attached claims. For instance, the details of the implemen¬ tation of the filter block realized by a processor for performing the same functions may vary. The solution according to the invention is not either necessarily limited to the generation of the clock signal of a node in a digital telecommunication network, but other applications of the same type are possible as well.

Claims

Claims :

1. Method of generating a clock signal (CLK) by means of a phase-locked loop comprising a phase com- parator (101), a loop filter (102), and a voltage- controlled oscillator (105), wherein a synchronizing signal (MCLK) derived from a synchronization source is applied to a first input in the phase comparator (101), and the clock signal is locked to the synchron- izing signal, the locking of the loop being speeded up by increasing the bandwidth of the loop, c h a r a c¬ t e r i z e d in that changes in a control voltage (Vc3) of the oscillator (105) are prevented tempor¬ arily in response to a change where a currently applied synchronizing signal becomes inadequate for use in timing, and that the bandwidth of the loop is increased temporarily in response to a change where a synchronizing signal adequate for use in timing is again taken into use.

2. Method according to claim 1, c h a r a c¬ t e r i z e d in that changes in the control voltage (Vc3) of the oscillator (105) are prevented and the bandwidth of the loop is increased by connecting an analog-to-digital converter (103), a digital lowpass filter (107) and a digital-to-analog converter (104) between the loop filter (102) and the oscillator (105), whereby the change of the control voltage is prevented by freezing the output signal of the digital-to-analog converter (104) substantially to its current value, and the bandwidth of the loop is in¬ creased temporarily by connecting the control signal present in the output of the analog-to-digital converter to said digital-to-analog converter (104) while bypassing the digital lowpass filter (107).

3. Method according to claim 2, c h a r a c- t e r i z e d in that the digital value of the control voltage of the oscillator (105) is stored at regular intervals in a memory (111), and that the freezing of the output signal of the digital-to-analog converter (104) is performed by connecting the value stored in the memory to the input of the digital-to- analog converter (104).

4. Method according to claim 1 or 3, wherein a clock signal for a node in a digital telecommunication network is derived from a master clock signal (MCLK) originating from the master node of the network, c h a r a c t e r i z e d in that said change informa¬ tion is obtained from line interface circuits (114) of the node.

5. Phase-locked loop for generating a clock signal, comprising a phase comparator (101), a loop filter (102), and a voltage-controlled oscillator (105), a synchronizing signal (MCLK) from a synchron¬ ization source being connected to an input in the phase comparator (101), and the clock signal being locked to the synchronizing signal, c h a r a c¬ t e r i z e d in that it comprises a combination of

- means (108, 109, 110, 111) for temporarily preventing changes in a control voltage (Vc3) of the oscillator (105) in response to a change where a currently applied synchronizing signal becomes in¬ adequate for use in timing; and

- means (108-110) for temporarily increasing the bandwidth of the loop in response to a change where a synchronizing signal adequate for use in timing is again taken into use.

6. Phase-locked loop according to claim 5, c h a r a c t e r i z e d in that said means comprise a block positioned between the loop filter (102) and the oscillator (105) and comprising in succession an analog-to-digital converter (103), a processor (106) having a memory (111) and a digital lowpass filter (107), and a digital-to-analog converter (104).

7. Phase-locked loop according to claim 6, c h a r a c t e r i z e d in that said means for preventing changes in the control voltage (Vc3) of the oscillator (105) comprise said memory (111), a selector (110) having an input to which the output signal of the memory is connected, and said digital- to-analog converter (104) having an input to which the output of the selector (110) is connected.

8. Phase-locked loop according to claim 7, c h a r a c t e r i z e d in that said means for increasing the bandwidth of the loop comprise said selector (110), to the respective inputs of which the output of the digital lowpass filter (107) and the output of the analog-to-digital converter (103) are connected, and the output of which is connected to the input of the digital-to-analog converter (104).

9. Phase-locked loop according to claim 6, by means of which a clock signal for a node in a digital telecommunication network is derived from a master clock signal (MCLK) originating from the master node of the network, c h a r a c t e r i z e d in that the processor (106) is connected to line interface cir¬ cuits (114) of the node for applying said change information to the processor.