FI85927B - FAONGKOPPLING FOER AOTERVINNANDE AV BAERVAOGEN UR EN QAM-SIGNAL. - Google Patents

Description

1 85927

Interception circuit for carrier reconstruction from the QAM signal

The invention relates to an interception circuit for reconstructing a carrier from a QAM signal in a demodulation circuit comprising a demodulator of a digital radio system and a clock regeneration circuit comprising a voltage controlled oscillator (VCO) and a control voltage generator.

The general structure of such a radio system with its transmitting and receiving devices is described in the article "140-Mbit / s-Modem for Digital-Digital Systems with 16 QAM", H. Barth and J.A. Nossek, Telcom Report 6 (1983), No. 5, p. 271-276. In this case, the required quadrature carriers are produced by a 140 MHz oscillator and a 90 ° branching unit, whereby the phase of the oscillator signal is monitored by means of a synchronized control loop.

In demodulation switching for a quadrature amplitude modulated signal, it is necessary that the phase of the carrier synchronizes with the phase of the QAM signal. However, after the QAM signal is interrupted, there may be a difference (frequency deviation) between the carrier frequency of the input signal and the VCO frequency. This is due to the tolerance of the carrier frequency produced in the modulator, the relay error in the radioin connection, the tolerance of VC0 or the deviation in the production of the control voltage, which errors can be affected by normal variations in ambient temperature and operating voltage.

Due to this frequency deviation and the relatively low bandwidth of the control loop (which is necessary for the regeneration of a sufficiently vibration-free carrier signal), the capture circuit must often be adapted to affect the oscillation of the VC0.

2 85927 After the return of the QAM signal, it may then occur that certain capture deviations occur in certain frequency deviations11a.

The object of the invention is to provide a interception circuit which prevents or eliminates such prohibited interceptions.

According to the invention, this object is solved by connecting an input level monitoring unit to the demodulation circuit and a monitoring circuit connected to the output side for the bit error portion. the bit error torque switching causes the second switch 1 to switch so that the sweep voltage of the sweep oscillator can propagate to the voltage-controlled oscillator as long as the bit error rate of the switch is too large due to the lack of synchronization, and by which the sweep oscillation with respect to the symmetrical sweep voltage.

In a further preferred embodiment of the invention, there is an arrangement in which, when the input level falls below the error threshold, the VCO control voltage is set to zero and further has a counter for detecting the number of synchronization attempts.

The invention is described in more detail below in connection with the embodiment shown in the drawing.

Fig. 1 shows the capture circuit as a block diagram and Fig. 2 graphically shows the voltage at the output of VCO as a function of time.

3,85927

Figure 1 shows a demodulation circuit by means of a regeneration circuit of a demodulator D arranged in the transmission path and a carrier consisting of a voltage-controlled oscillator VCO and a control voltage generating unit TR. Before the demodulator D, an input level monitoring unit P and a 1 output side 1 e monitoring circuit F are connected for the bit error portion (for monitoring the opening of the eye, a code error or the like). The input level monitoring unit P and the bit error knockout circuit F are connected to a logic L which is connected to the control voltage generating unit TR via two electronic switches S1, S2. The connection further includes a sweep oscillator W connected to both the logic L and the second electronic switch S2.

The description of the mode of action of the capture circuit below is also served by Figure 2, which shows the time dependence of the input voltage of VC0. In this case, the course of the sweep voltage is plotted in the presence of an offset (frequency deviation) (U at value II)

WJI

and in the same case that there is no offset ia (U

WI

value I). III could be the value of the control voltage at which synchronization can occur, the bricks and 12:11 a are the time zones in which the control loop is cut off when the offset is noi la. In these time zones, the input voltage of VC0 in each case follows the course of the sweep voltage. The point of intersection of the voltage flow in the change from U to U with the value III then WI mi i then forms the synchronization time T.

The interception circuit operates in such a way that when the input level falls below the error threshold, the logic L controls the switch SI so that the control voltage generating unit TR outputs a zero-symmetrical sweep voltage or optionally zero control voltage, whereby the frequency deviation is as small as possible. By means of the logic L, the switching of the bit errors is caused by the logic L of the switch S2, so that the scanning voltage of the scanning oscillator W can propagate to the input of VC0 as long as the bit error rate is too high, 4 85927 i.e. no synchronization has occurred. If an incorrect interception1a occurs, the kneading circuit remains in the alarm position and the sweep voltage remains 1fired. To eliminate the error capture1, at each minimum and maximum value of the sweep voltage, logic is made to control the switch SI so that the control loop is broken and the offset of the VCO control voltage is removed. However, the sweep voltage remains affected. The event is repeated periodically until the pacing is correct.

Thus, in the circuit according to the invention, in order to achieve the synchronization of the recovered carrier signal, the sweep voltage arranged with the QAM signal during the maximum and minimum values has an offset shift of the VC0 (for producing a carrier signal) and a control loop break as long as the correct interception is not generated. In addition, in the absence of a QAM signal, the frequency deviation of VC0 is kept as small as possible.

The connection may also be provided with a counter for the number of synchronization attempts. This allows each new synchronization attempt to be initiated with a modified circuit layout, e.g., a modified VCO offset'i11 a.

Claims (3)

A demodulation circuit consisting of a digital radio system demodulator and a voltage controlled oscillator (VCO) and a control voltage generator (DCO) and a synchronous regeneration circuit (TR) comprising a field switching demodulation circuit an input level control unit (P) and a control circuit (F) connected to the output side for the bit error portion, connected to a logic unit which controls the first switch (SI) when the input level falls below the error threshold so that the control voltage generating unit provides a zero-balanced sweep voltage the bit error monitoring circuit (F) causes the second switch (S2) to be switched through so that the scanning voltage of the scanning oscillator (W) can propagate to the voltage-controlled oscillator as long as the bit error portion is too large due to the lack of synchronization, and by which the sweep oscillator (W) in turn, depending on the value of its output voltage, in turn controls the first switch (SI) so that the control voltage generating unit gives a sweep voltage symmetrical with respect to zero. Interception circuit according to Claim 1, characterized in that when the input level falls below the error threshold, the VCO control voltage is controlled to zero. Capture circuit according to Claims 1 and 2, characterized in that it has a counter for detecting the number of synchronization attempts. 6 85927