GB2085623A

GB2085623A - Improvements in or Relating to Input-output Modules for Electronic Processors

Info

Publication number: GB2085623A
Application number: GB8127217A
Authority: GB
Original assignee: Italtel SpA; Italtel Societa Italiana Telecomunicazioni SpA
Current assignee: Italtel SpA
Priority date: 1980-09-09
Filing date: 1981-09-09
Publication date: 1982-04-28
Also published as: BR8105668A; FR2489986A1; IT8024540A0; IT1149252B; DE3135564A1

Abstract

An input-output module comprising a plurality of interface units IP1...IPn and circuits designed to control and operate the interface units by monitoring dialogue between a processor and peripheral units P1...Pn. The module includes circuits for establishing the priority of the various interfaces in the module; circuits for checking formal accuracy of the data flowing in the module bus, thereby preventing an error from being propagated to hierarchically higher structures; and circuits for processing module signallings to be sent to the central logic unit. <IMAGE>

Description

SPECIFICATION Improvements in or Relating to Input-Output Modules for Electronic Processors The present invention relates to an inputoutput module for an electronic processor, comprising a plurality of input-output interface units and auxiliary circuits.

Each interface unit constitutes a communication path between a central logic unit (CPU) in the processor and a peripheral unit for communication with the processor (or vice versa), and makes it possible to exchange data.

Data transfer operations between the central memory or the processor CPU and the peripheral units by way of interface circuits call for a series of instructions being carried out. To avoid engaging the CPU unnecessarily, it is convenient to delegate decentralized members to perform such operations, the decentralized members directly interacting with the interface circuits.

Such decentralized members, termed control units below, preferably have a simple structure which limits, however, the number of interface circuits each control unit can control. Thus, the input-output portion of the processor has a modular structure where each module comprises at least a plurality of interface units and one control unit arranged to operate them. A message sent to the CPU includes the address of the module, the address of the interface in the module and an instruction for the control unit to perform an operation by activating a suitable microprogramme.

According to the invention, there is provided an input-output module for an electronic processor comprising: a plurality of interface circuits connected in parallel with each other and to a bidirectional internal bus; means for monitoring a plurality of unidirectional channels arranged to connect the peripheral units directly to a central memory, a control unit arranged to generate micro-controls for carrying out input-output cycles in response to instructions sent by a central logic unit through a control bus; a data interface unit arranged to be connected via a bidirectional data bus to the central logic unit and connected to a pair of unidirectional internal buses, a peripheral unit control unit arranged to generate the code of instructions to be carried out in response to messages sent by the central logic unit by way of the bidirectional data bus and one of the unidirectional buses, and to select the peripheral unit to which the said code is to be sent, the control unit also being arranged to generate a request code which is sent to the central logic unit by way of a bidirectional control bus in response to a request sent by one of the interface circuits, or by the means for monitoring the channels for direct access of the peripheral units to the central memory; a termination unit arranged to control error signallings generated by other circuits in the module and by it own control circuits so as to generate a request to be transmitted to the central logic unit by way of the peripheral unit control unit; a bus disconnecting unit arranged to disconnect from one another the two unidirectional buses and to connect them to the bidirectional bus to which the interface units and the termination unit are connected; and a priority unit arranged to send to the peripheralunit control unit the code of one of the interface units and the direct memory access means of highest priority requiring to be connected to the central logic unit, thereby enabling a respective request to be generated.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which:~ Figure 1 shows a block diagram of a module constituting a preferred embodiment of the present invention; Figure 2 shows control circuits for checking formal correctness of data; Figure 3 shows priority establishing circuits; Figure 4 shows a simplified block diagram of a termination unit UT; and Figure 5 shows a simplified block diagram of a peripheral-unit monitoring unit UGP.

The block diagram shown in Figure 1 comprises the following functional blocks: a control interface IC which deals with the signals governing signalling and/or instruction exchange between the CPU and the module by way of the control bus BE; a module control unit UCM designed to execute the various input-output cycles to generate microcontrols MO which are generally indicated by COM in the drawings along with the instructions generated by the control interface IC and control the other members of the module; an embodiment of the unit UCM is disclosed in the Italian Patent Application No.

24406 A/80 filed on September 2, 1980; peripheral interface units IP (IP" . . ., IPn) which constitute a connection line between the CPU and the peripheral units P; an embodiment of such peripheral interfaces is disclosed in the Italian Patent Application No. 24284 A/80 filed on August 26, 1 980; a priority unit UP designed to identify the unit of highest priority among the peripheral units sending a request I, thereby assigning maximum priority to the error signalling request in the inputoutput module; a data interface ID which connects a general bus GB to unidirectional buses IDB and ODB; a direct memory access unit DMA designed to monitor a plurality of unidirectional channels for direct access to the central memory; an embodiment thereof is illustrated in the Italian Patent Application No. 23650 A/80 filed on July 24,1980; a peripheral-unit control unit UGB designed to generate a selection signal SI for peripheral interfaces and the operative code Cl of the instructions to be carried out and to generate, in response to the request of highest priority, a request code RIC to be sent to the CPU by way of the control interface IC and the control bus BE; a termination unit UT designed to deal with error signallings generated in the module; this unit comprises a control register and a module state register similar to those provided in the interface unit IP; and a bus disconnecting unit UDB arranged to disconnect the buses ODB and IDB which are connected to the bidirectional bus IOB to which the interface IP and the termination unit UT are connected.

Figure 2 diagrammatically shows a data interface unit ID, a bus disconnecting unit UDB and a portion of a termination unit UT designed to control formal correctness of data.

Each data word comprises a predetermined number of significant bits followed by at least one parity bit. The diagram in Figure 2 illustrates circuits designed to check formal correctness of data exchanged with the CPU.

The significant bits of the data sent along the bus IOB by a peripheral interface IP are sent to parity generating circuits GP1 and GP2 respectively belonging to data interface ID and the termination unit UT which also receives the parity bits sent by the IP. The parity bits PA generated by the circuit GP2 are compared by the circuit CP3 in the termination unit UT with those sent by the interface IP, thereby producing analarm IOE, if necessary, and compared by the circuit CP2 in the data interface ID to those provided by the circuit GP,, thereby producing an alarm IBE, if necessary.

As the peripheral interfaces IP are also provided with parity controlling circuits (not shown in the drawings), a possible error is signalled by the peripheral interface IP and by the termination unit UT but cannot be propagated to the CPU since the datum parity is regenerated by the circuit GP1, compared by the data interface ID to heat generated by the circuit GP, and added to the significant bits (produced by the interface IP) before the datum is sent to the CPU through the general bus GB.

The data from the general bus GB are parity controlled by the circuit CB, in the data interface ID which can then generate an error signal GBE, by the circuit CP3 in the termination unit UT which compares their parity to that given by the circuit GP2, thereby generating a possible error signal IOE, and by the parity control circuits in the same interface in the case where such data are to be sent to peripheral interface IP. Thus, an erroneous datum from the general bus GB activates the control circuits of all components of the module from which it comes.

The termination unit UT exchanges data with the general bus GB from which it recieves a control word which is written in the control register, and to which it sends the content of the state register. The control word is controlled by the circuits CP1 and CP3 according to the previously illustrated procedure. The content of the state register is sent through the buses IOB and IDB to the generator GP2 in the termination unit UT which generates the parity PA thereof for the circuit CP2 (the circuit CP3 being cut off).

All error signals generated within the module are sent to the termination unit UT where they are stored in the state register and cause messages for the CPU to be generated. All data and control transmissions along the general bus GB and the control bus BE are effected through line drivers D and line receivers R, as is also indicated for the data in the drawing. Thus, the control interface IC comprises drivers and receivers for exchanging signals with the CPU.

The circuit arrangements which makes it possible to spot the request of highest priority among the requests I received from the peripheral interfaces IP is described with reference to the diagram of Figure 3. Such a circuit arrangement comprises a plurality of decentralized circuits PC provided in all the peripheral interfaces IP and in the termination unit UT, and a centralized portion indicated by a block UP and a partial block UGP in the drawings.

A request RQ generated within the peripheral interface IP sets, in the absence of a signal I, a bistable FB and (at the first pulse of a synchronization clock FS) the bistable FF which generates the request I thereby disabling a gate 1 and enabling a gate 2. All requests I are sent to a priority coder PE which provides the codes associated with its input of highest priority at each instant. Such a code is stored in a register PRR and sent to a decoder DEC which activates the wire SI to interface IP of highest priority, thereby enabling it.

In the interface IP, the signal SI passes through the gate 2 to generate a request signal IRQ which lasts until the CPU accedes to the request and sends a signal LAK, or until another interface of highest priority activates its signal I.

The arrival of the coder PE of a signal I transmitted by an interface of higher priority causes the signal SI (and thus the signal IRQ) to fall, whereas the request I remains pending and will be met as soon as the CPU has met the requests from the devices of highest priority.

The DMA requests generated by the interface units are of highest priority than the request I. The DMA requests are supplied to a priority coder PD whose output DP controls a multiplexer MX through which it is connected to a register PRR as soon as the CPU has terminated the cycle being executed in the instant in which a DMA request is generated.

The module itself has access to the coders PE and PD by way of the termination unit UT and occupies the coder input to which maximum priority is assigned.

Thus, the module request always has highest priority.

The priority of an interface depends only on its physical position in the module and the correct operation of the priority circuit is independent of the actual presence of all printed circuit boards carrying the interface circuits. In this way one of the main drawbacks of a circuit arrangement of known type in which a signal is propagated from one circuit to another starting from that of highest priority and stopping when a request is found, is eliminated. Such a circuit arrangement, besides being slower as it is necessary to take into account the signal propagation time, requires all circuit boards to be present, or the circuit boards which may have been removed for any reason to be replaced by suitable boards to ensure electrical continuity of the priority circuits.

According to a preferred embodiment the priority coders PE, PD for the requests I and the requests DMA, and the multiplexer MX form a block UP (Figure 1), whereas the register PRR and the decoder DEC are included in the control unit for the peripheral units ugp.

Figure 4 shows a simplified block diagram of the termination unit UT.

A control word sent by the CPU to characterize the module, thereby enabling it, or not, to perform certain functions, DMA, etc., reaches the bus IOB, is parity controlled (GP2, GP3, alarm signal IOE) and written in the register RCM upon control from the CPU.

The alarm signals generated by all the selfcontrol members with the functional units forming the module are provided, are sent to the state register RSM where they are stored. The presence of at least one alarm activates an adder S which generates a signal RQ for the priority circuit PC which is not illustrated in detail as it is substantially similar to that provided in the interface circuits IP in Figure 3.

The CPU may call for the content of the state register (state word) through the buses IOB, IB and GB.

The termination unit also comprises a decoder DEM which is arranged to activate one of its outputs UST in response to an operative code CI of the instructions the module must carry out.

Both the decoder DEM and the priority circit CP are enabled by the presence of a signal on the wire SI.

Figure 5 shows a simplified block diagram of the control unit for the peripheral units UGP, the block diagram including:~ a register SCR arranged to store the addresses received from CPU through the buses GB and ODB; such addresses are decoded by the decoder DEC to which the register PRR is connected, thereby activating one of the selection wires SI (Figure 3); a register ISR arranged to store the operative code CI of the instructions sent to the module of the CPU; a request generating logic unit SRQ which generates request RIC to be sent to the CPU in response to the requests IRQ generated by the module or by the interfaces and to the DMA requests (DRQ).

According to a preferred embodiment, the logic unit SRQ comprises a ROM addressed by the requests IRQ and DRQ.

Various modifications may be made within the scope of the invention. By way of example, it is possible to gather in a single functional unit the centralized components (PE, PD, MX, PRR, DEC) of the priority circuit or the register ISR and the decoder DEM.

Claims

1. An input-output module for an electronic processor, comprising: a plurality of interface circuits connected in parallel with each other and to a bidirectional internal bus; means for monitoring a plurality of unidirectional channels arranged to connect the peripheral units directly to a central memory, a control unit arranged to generate microcontrols for carrying out inputoutput cycles in response to instructions sent by a central logic unit, through a control bus; a data interface unit arranged to be connected via a bidirectional data bus to the central logic unit and connected to a pair of unidirectional internal buses; a peripheral-unit control unit arranged to generate the code of instructions to be carried out in response to messages sent by the central logic unit by way of the bidirectional data bus and one of the unidirectional buses, and to select the peripheral unit to which the said code is to be sent, the control unit also being arranged to generate a request code which is sent to the central logic unit by way of a bidirectional control bus in response to a request sent by one of the interface circuits, or by the means for monitoring the channels for direct access of the peripheral units to the central memory; a termination unit arranged to control error signallings generated by other circuits in the module and by its own control circuits, so as to generate a request to be transmitted to the central logic unit by way of the peripheral-unit control unit; a bus disconnecting unit arranged to disconnect from one another the two unidirectional buses and to connect them to the bidirectional bus to which the interface units and the termination unit are connected; and a priority unit arranged to send to the peripheralunit control unit the code of the one of the interface units and/the direct memory access means of highest priority requiring to be connected to the central logic unit, thereby enabling a respective request to be generated.

2. A input-output module as claimed in claim 1, in which the termination unit is arranged to accede to the priority unit having the highest priority, the direct memory access means having a higher priority than the interface unit and the priority order among the interface units and among the direct-memory access means being determined only by their positions in a frame.

3. An input-output module as claimed in claim 1 or 2, in which the data interface comprises: at least one line driver line receiver pair arranged to disconnect from one another the two unidirectional buses and to connect them to the data bus; a first parity control circuit arranged to check formal correctness of data coming from the data bus and to generate a first error signal; a first parity generator arranged to generate, in response to the significant bits of a data word from the bidirectional bus, at least one parity bit which is added to the significant bits before sending the data word to the data bus; and a second parity control circuit arranged to compare the output of the first parity generator with the bit or bits generated by the termination unit, and to generate a second error signal.

4. An input-output module as claimed in any one of the preceding claims, in which the termination unit and the interface units comprise a priority circuit comprising: a first bistable arranged to be sent by the signal at the output of a first gate whose first input is arranged to receive a request signal generated in the termination or interface unit; a second bistable having a data input connected to the output of the first bistable, a timing input connected to a synchronization clock and an output connected to a second inverted input of the first gate and to a first input of a second gate; the second gate which has a second input connected to the output of the first bistable and a third input connected to the selection wire of the interface unit or the termination unit, the output signal of the second gate constituting the request sent to the peripheral-unit control unit; and a third gate arranged to be enabled by the signal available on the selection wire of the interface unit or the termination unit to allow a signal generated by the central logic unit to pass after a request has been met to reset the first bistable, the outputs of all the priority circuits being connected to the inputs of a first priority coder whose output is connected to a first input of a multiplexer whose second input is connected to the output of a second priority coder whose inputs are arranged to receive the direct memory access requests generated by the interface unit, the output of the multiplexer being connected via a first register to a first decoder which activates one of the selection wires.

5. A input-output module as claimed in claim 4, when dependent on claim 2, in which the output of the termination unit is connected to the highest priority inputs of the first priority coder and the second priority coder.

6. An input-output module as claimed in claim 4, when dependent on claim 3, in which the termination unit comprises: a second parity generator circuit arranged to generate, in response to the significant bits of a data word from the bidirectional bus, at least one parity bit sent to the second parity control circuit of the data interface unit and to a third parity control circuit; the third parity control circuit which is arranged to compare the output of the second parity generating circuit with the parity bit or bits of the data word from the bidirectional bus and to generate a third error signal; a control register arranged to store a control word from the central logic unit; a state register arranged to store the error signals generated within the module and whose content is sent to the central logic unit in response to an instruction by the central logic unit; an adder circuit arranged to generate the request signal for the priority circuit in response to the presence of at least one error stored in the state register; and a second decoder arranged to be enabled by the signal available on the selection wire of the termination unit and arranged to decode the code of the instruction stored in the peripheral-unit control unit.

7. A input-output module as claimed in claim 6, in which the peripheral-unit control unit comprises: a first register; a second register arranged to store the addresses sent to the module by the central logic unit by way of the data bus; a first decoder whose inputs are connected to the outputs of the first and second registers; a third register arranged to store the codes of the instructions sent to the module by the central logic unit; and a request generating logic unit arranged to generate a request code to be sent to the central logic unit in response to the requests generated by the interface unit and the termination unit and to the requests sent by the direct memory access means.

8. An input-output module as claimed in any one of the preceding claims, in which the request generating logic unit comprises a read only memory arranged to be addressed by the said requests.

9. A input-output module substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

10. An electronic processor including a module as claimed in any one of the preceding claims.